Carrier transport in amorphous SiC/crystalline silicon heterojunctions

A. N. Nazarov, Ya N. Vovk, V. S. Lysenko, V. I. Turchanikov, V. A. Scryshevskii, S. Ashok

Research output: Contribution to journalArticle

17 Citations (Scopus)

Abstract

Charge carrier transport in chemical vapor-deposited amorphous SiC/p-type crystalline Si heterostructures has been studied over the temperature range 80-400 K, using current-voltage (I-V), current-temperature (I-T), capacitance-voltage (C-V), and capacitance relaxation (C-t) characteristics. These heterojunctions exhibit high breakdown voltages (230 V) and a diode rectification ratio of 103 at ±0.5 V. At low temperatures (80-120 K) the a-SiC behaves like a dielectric, and the interface built-in voltage can be determined from the capacitance-voltage plot. The corresponding low forward bias current flow is limited by variable-range electron hopping conductivity at Fermi level in the a-SiC layer. At increasing temperature and forward bias voltage, an additional hole current component is found with the transport governed by a multistep tunneling hole emission process through the a-SiC/c-Si heterobarrier. At still higher forward bias voltages (>0.8 V), space-charge-limited hole conduction in the presence of traps in the a-SiC bulk limits transport.

Original languageEnglish (US)
Pages (from-to)4422-4428
Number of pages7
JournalJournal of Applied Physics
Volume89
Issue number8
DOIs
StatePublished - Apr 15 2001

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heterojunctions
electric potential
silicon
capacitance
rectification
electrical faults
temperature
charge carriers
space charge
plots
diodes
traps
vapors
conduction
conductivity
electrons

All Science Journal Classification (ASJC) codes

  • Physics and Astronomy(all)

Cite this

Nazarov, A. N., Vovk, Y. N., Lysenko, V. S., Turchanikov, V. I., Scryshevskii, V. A., & Ashok, S. (2001). Carrier transport in amorphous SiC/crystalline silicon heterojunctions. Journal of Applied Physics, 89(8), 4422-4428. https://doi.org/10.1063/1.1355698
Nazarov, A. N. ; Vovk, Ya N. ; Lysenko, V. S. ; Turchanikov, V. I. ; Scryshevskii, V. A. ; Ashok, S. / Carrier transport in amorphous SiC/crystalline silicon heterojunctions. In: Journal of Applied Physics. 2001 ; Vol. 89, No. 8. pp. 4422-4428.
@article{ecefe19447ae41f8a52f0cee5539187c,
title = "Carrier transport in amorphous SiC/crystalline silicon heterojunctions",
abstract = "Charge carrier transport in chemical vapor-deposited amorphous SiC/p-type crystalline Si heterostructures has been studied over the temperature range 80-400 K, using current-voltage (I-V), current-temperature (I-T), capacitance-voltage (C-V), and capacitance relaxation (C-t) characteristics. These heterojunctions exhibit high breakdown voltages (230 V) and a diode rectification ratio of 103 at ±0.5 V. At low temperatures (80-120 K) the a-SiC behaves like a dielectric, and the interface built-in voltage can be determined from the capacitance-voltage plot. The corresponding low forward bias current flow is limited by variable-range electron hopping conductivity at Fermi level in the a-SiC layer. At increasing temperature and forward bias voltage, an additional hole current component is found with the transport governed by a multistep tunneling hole emission process through the a-SiC/c-Si heterobarrier. At still higher forward bias voltages (>0.8 V), space-charge-limited hole conduction in the presence of traps in the a-SiC bulk limits transport.",
author = "Nazarov, {A. N.} and Vovk, {Ya N.} and Lysenko, {V. S.} and Turchanikov, {V. I.} and Scryshevskii, {V. A.} and S. Ashok",
year = "2001",
month = "4",
day = "15",
doi = "10.1063/1.1355698",
language = "English (US)",
volume = "89",
pages = "4422--4428",
journal = "Journal of Applied Physics",
issn = "0021-8979",
publisher = "American Institute of Physics Publising LLC",
number = "8",

}

Nazarov, AN, Vovk, YN, Lysenko, VS, Turchanikov, VI, Scryshevskii, VA & Ashok, S 2001, 'Carrier transport in amorphous SiC/crystalline silicon heterojunctions', Journal of Applied Physics, vol. 89, no. 8, pp. 4422-4428. https://doi.org/10.1063/1.1355698

Carrier transport in amorphous SiC/crystalline silicon heterojunctions. / Nazarov, A. N.; Vovk, Ya N.; Lysenko, V. S.; Turchanikov, V. I.; Scryshevskii, V. A.; Ashok, S.

In: Journal of Applied Physics, Vol. 89, No. 8, 15.04.2001, p. 4422-4428.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Carrier transport in amorphous SiC/crystalline silicon heterojunctions

AU - Nazarov, A. N.

AU - Vovk, Ya N.

AU - Lysenko, V. S.

AU - Turchanikov, V. I.

AU - Scryshevskii, V. A.

AU - Ashok, S.

PY - 2001/4/15

Y1 - 2001/4/15

N2 - Charge carrier transport in chemical vapor-deposited amorphous SiC/p-type crystalline Si heterostructures has been studied over the temperature range 80-400 K, using current-voltage (I-V), current-temperature (I-T), capacitance-voltage (C-V), and capacitance relaxation (C-t) characteristics. These heterojunctions exhibit high breakdown voltages (230 V) and a diode rectification ratio of 103 at ±0.5 V. At low temperatures (80-120 K) the a-SiC behaves like a dielectric, and the interface built-in voltage can be determined from the capacitance-voltage plot. The corresponding low forward bias current flow is limited by variable-range electron hopping conductivity at Fermi level in the a-SiC layer. At increasing temperature and forward bias voltage, an additional hole current component is found with the transport governed by a multistep tunneling hole emission process through the a-SiC/c-Si heterobarrier. At still higher forward bias voltages (>0.8 V), space-charge-limited hole conduction in the presence of traps in the a-SiC bulk limits transport.

AB - Charge carrier transport in chemical vapor-deposited amorphous SiC/p-type crystalline Si heterostructures has been studied over the temperature range 80-400 K, using current-voltage (I-V), current-temperature (I-T), capacitance-voltage (C-V), and capacitance relaxation (C-t) characteristics. These heterojunctions exhibit high breakdown voltages (230 V) and a diode rectification ratio of 103 at ±0.5 V. At low temperatures (80-120 K) the a-SiC behaves like a dielectric, and the interface built-in voltage can be determined from the capacitance-voltage plot. The corresponding low forward bias current flow is limited by variable-range electron hopping conductivity at Fermi level in the a-SiC layer. At increasing temperature and forward bias voltage, an additional hole current component is found with the transport governed by a multistep tunneling hole emission process through the a-SiC/c-Si heterobarrier. At still higher forward bias voltages (>0.8 V), space-charge-limited hole conduction in the presence of traps in the a-SiC bulk limits transport.

UR - http://www.scopus.com/inward/record.url?scp=0035870896&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0035870896&partnerID=8YFLogxK

U2 - 10.1063/1.1355698

DO - 10.1063/1.1355698

M3 - Article

AN - SCOPUS:0035870896

VL - 89

SP - 4422

EP - 4428

JO - Journal of Applied Physics

JF - Journal of Applied Physics

SN - 0021-8979

IS - 8

ER -

Nazarov AN, Vovk YN, Lysenko VS, Turchanikov VI, Scryshevskii VA, Ashok S. Carrier transport in amorphous SiC/crystalline silicon heterojunctions. Journal of Applied Physics. 2001 Apr 15;89(8):4422-4428. https://doi.org/10.1063/1.1355698