Cash: Compiler assisted hardware design for improving DRAM energy efficiency in CNN inference

Anup Sarma, Huaipan Jiang, Ashutosh Pattnaik, Jagadish Kotra, Mahmut Taylan Kandemir, Chita R. Das

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The advent of machine learning (ML) and deep learning applications has led to the development of a multitude of hardware accelerators and architectural optimization techniques for parallel architectures. This is due in part to the regularity and parallelism exhibited by the ML workloads, especially convolutional neural networks (CNNs). However, CPUs continue to be one of the dominant compute fabric in data-centers today, thereby also being widely deployed for inference tasks. As CNNs grow larger, the inherent limitations of a CPU-based system become apparent, specifically in terms of main memory data movement. In this paper, we present CASH, a compiler-assisted hardware solution that eliminates redundant data-movement to and from the main memory and, therefore, reduces main memory bandwidth and energy consumption. Our experimental evaluations on a set of four different state-of-the-art CNN workloads indicate that CASH provides, on average, ∼40% and ∼18% reductions in main memory bandwidth and energy consumption, respectively.

Original languageEnglish (US)
Title of host publicationMEMSYS 2019 - Proceedings of the International Symposium on Memory Systems
PublisherAssociation for Computing Machinery
Pages396-408
Number of pages13
ISBN (Electronic)9781450372060
DOIs
StatePublished - Sep 30 2019
Event2019 International Symposium on Memory Systems, MEMSYS 2019 - Washington, United States
Duration: Sep 30 2019Oct 3 2019

Publication series

NameACM International Conference Proceeding Series

Conference

Conference2019 International Symposium on Memory Systems, MEMSYS 2019
CountryUnited States
CityWashington
Period9/30/1910/3/19

All Science Journal Classification (ASJC) codes

  • Software
  • Human-Computer Interaction
  • Computer Vision and Pattern Recognition
  • Computer Networks and Communications

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    Sarma, A., Jiang, H., Pattnaik, A., Kotra, J., Kandemir, M. T., & Das, C. R. (2019). Cash: Compiler assisted hardware design for improving DRAM energy efficiency in CNN inference. In MEMSYS 2019 - Proceedings of the International Symposium on Memory Systems (pp. 396-408). (ACM International Conference Proceeding Series). Association for Computing Machinery. https://doi.org/10.1145/3357526.3357536