Characterization and modeling of run-time techniques for leakage power reduction

Yuh Fang Tsai, David E. Duarte, N. Vijaykrishnan, Mary Jane Irwin

Research output: Contribution to journalArticlepeer-review

36 Scopus citations


While some leakage power reduction techniques require modification of the process technology, others are based on circuit-level optimizations and are applied at run-time. We focus our study on the latter and compare three techniques: input vector control, body bias control, and power supply gating. We determine their limits and benefits in terms of the potential leakage reduction, performance penalty, and area and power overhead. The leakage power savings trends considering technology scaling are also presented. Due to the differences in the properties of datapath logic and memory structures, different implementations are recommended. Finally, the use of the "minimum idle time" parameter, as a metric for evaluating different leakage control mechanisms, is showed.

Original languageEnglish (US)
Pages (from-to)1221-1232
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number11
StatePublished - Nov 2004

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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