Characterizing dynamic and leakage power behavior in flip-flops

R. Ramanarayanan; N. Vijaykrishnan; M. J. Irwin

doi:10.1109/ASIC.2002.1158098

Characterizing dynamic and leakage power behavior in flip-flops

R. Ramanarayanan, N. Vijaykrishnan, M. J. Irwin

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

16 Scopus citations

Abstract

This paper presents a detailed analysis of power consumption in a variety of flip-flop designs including scannable latches. The analysis was performed by implementing and simulating the different designs using 70 nm, IV CMOS technology. First, we perform a detailed characterization of the dynamic power consumption due to output transitions and that due to clock and data transitions when there is no output transition. Further, we also characterize the leakage behavior of each of the flip-flop designs and specifically, characterize the input dependence of leakage.

Original language	English (US)
Title of host publication	Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
Editors	John Chickanosky, Ram K. Krishnamurthy, P.R. Mukund
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	433-437
Number of pages	5
ISBN (Electronic)	0780374940
DOIs	https://doi.org/10.1109/ASIC.2002.1158098
State	Published - Jan 1 2002
Event	15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, United States Duration: Sep 25 2002 → Sep 28 2002

Publication series

Name	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
Volume	2002-January
ISSN (Print)	1063-0988

Other

Other	15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
Country/Territory	United States
City	Rochester
Period	9/25/02 → 9/28/02

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ASIC.2002.1158098

Cite this

Ramanarayanan, R., Vijaykrishnan, N., & Irwin, M. J. (2002). Characterizing dynamic and leakage power behavior in flip-flops. In J. Chickanosky, R. K. Krishnamurthy, & P. R. Mukund (Eds.), Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 (pp. 433-437). [1158098] (Proceedings of the Annual IEEE International ASIC Conference and Exhibit; Vol. 2002-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASIC.2002.1158098

Ramanarayanan, R. ; Vijaykrishnan, N. ; Irwin, M. J. / Characterizing dynamic and leakage power behavior in flip-flops. Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. editor / John Chickanosky ; Ram K. Krishnamurthy ; P.R. Mukund. Institute of Electrical and Electronics Engineers Inc., 2002. pp. 433-437 (Proceedings of the Annual IEEE International ASIC Conference and Exhibit).

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abstract = "This paper presents a detailed analysis of power consumption in a variety of flip-flop designs including scannable latches. The analysis was performed by implementing and simulating the different designs using 70 nm, IV CMOS technology. First, we perform a detailed characterization of the dynamic power consumption due to output transitions and that due to clock and data transitions when there is no output transition. Further, we also characterize the leakage behavior of each of the flip-flop designs and specifically, characterize the input dependence of leakage.",

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Ramanarayanan, R, Vijaykrishnan, N & Irwin, MJ 2002, Characterizing dynamic and leakage power behavior in flip-flops. in J Chickanosky, RK Krishnamurthy & PR Mukund (eds), Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002., 1158098, Proceedings of the Annual IEEE International ASIC Conference and Exhibit, vol. 2002-January, Institute of Electrical and Electronics Engineers Inc., pp. 433-437, 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002, Rochester, United States, 9/25/02. https://doi.org/10.1109/ASIC.2002.1158098

Characterizing dynamic and leakage power behavior in flip-flops. / Ramanarayanan, R.; Vijaykrishnan, N.; Irwin, M. J.

Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. ed. / John Chickanosky; Ram K. Krishnamurthy; P.R. Mukund. Institute of Electrical and Electronics Engineers Inc., 2002. p. 433-437 1158098 (Proceedings of the Annual IEEE International ASIC Conference and Exhibit; Vol. 2002-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - This paper presents a detailed analysis of power consumption in a variety of flip-flop designs including scannable latches. The analysis was performed by implementing and simulating the different designs using 70 nm, IV CMOS technology. First, we perform a detailed characterization of the dynamic power consumption due to output transitions and that due to clock and data transitions when there is no output transition. Further, we also characterize the leakage behavior of each of the flip-flop designs and specifically, characterize the input dependence of leakage.

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Ramanarayanan R, Vijaykrishnan N, Irwin MJ. Characterizing dynamic and leakage power behavior in flip-flops. In Chickanosky J, Krishnamurthy RK, Mukund PR, editors, Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. Institute of Electrical and Electronics Engineers Inc. 2002. p. 433-437. 1158098. (Proceedings of the Annual IEEE International ASIC Conference and Exhibit). doi: 10.1109/ASIC.2002.1158098

Characterizing dynamic and leakage power behavior in flip-flops

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