Characterizing dynamic and leakage power behavior in flip-flops

R. Ramanarayanan, N. Vijaykrishnan, M. J. Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Scopus citations

Abstract

This paper presents a detailed analysis of power consumption in a variety of flip-flop designs including scannable latches. The analysis was performed by implementing and simulating the different designs using 70 nm, IV CMOS technology. First, we perform a detailed characterization of the dynamic power consumption due to output transitions and that due to clock and data transitions when there is no output transition. Further, we also characterize the leakage behavior of each of the flip-flop designs and specifically, characterize the input dependence of leakage.

Original languageEnglish (US)
Title of host publicationProceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
EditorsJohn Chickanosky, Ram K. Krishnamurthy, P.R. Mukund
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages433-437
Number of pages5
ISBN (Electronic)0780374940
DOIs
StatePublished - Jan 1 2002
Event15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, United States
Duration: Sep 25 2002Sep 28 2002

Publication series

NameProceedings of the Annual IEEE International ASIC Conference and Exhibit
Volume2002-January
ISSN (Print)1063-0988

Other

Other15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
CountryUnited States
CityRochester
Period9/25/029/28/02

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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    Ramanarayanan, R., Vijaykrishnan, N., & Irwin, M. J. (2002). Characterizing dynamic and leakage power behavior in flip-flops. In J. Chickanosky, R. K. Krishnamurthy, & P. R. Mukund (Eds.), Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 (pp. 433-437). [1158098] (Proceedings of the Annual IEEE International ASIC Conference and Exhibit; Vol. 2002-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASIC.2002.1158098