Characterizing dynamic and leakage power behavior in flip-flops

R. Ramanarayanan, Vijaykrishnan Narayanan, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Abstract

This paper presents a detailed analysis of power consumption in a variety of flip-flop designs including scannable latches. The analysis was performed by implementing and simulating the different designs using 70 nm, IV CMOS technology. First, we perform a detailed characterization of the dynamic power consumption due to output transitions and that due to clock and data transitions when there is no output transition. Further, we also characterize the leakage behavior of each of the flip-flop designs and specifically, characterize the input dependence of leakage.

Original languageEnglish (US)
Title of host publicationProceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
EditorsJohn Chickanosky, Ram K. Krishnamurthy, P.R. Mukund
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages433-437
Number of pages5
ISBN (Electronic)0780374940
DOIs
StatePublished - Jan 1 2002
Event15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, United States
Duration: Sep 25 2002Sep 28 2002

Publication series

NameProceedings of the Annual IEEE International ASIC Conference and Exhibit
Volume2002-January
ISSN (Print)1063-0988

Other

Other15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
CountryUnited States
CityRochester
Period9/25/029/28/02

Fingerprint

Flip flop circuits
Electric power utilization
Clocks

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Ramanarayanan, R., Narayanan, V., & Irwin, M. J. (2002). Characterizing dynamic and leakage power behavior in flip-flops. In J. Chickanosky, R. K. Krishnamurthy, & P. R. Mukund (Eds.), Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 (pp. 433-437). [1158098] (Proceedings of the Annual IEEE International ASIC Conference and Exhibit; Vol. 2002-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASIC.2002.1158098
Ramanarayanan, R. ; Narayanan, Vijaykrishnan ; Irwin, Mary Jane. / Characterizing dynamic and leakage power behavior in flip-flops. Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. editor / John Chickanosky ; Ram K. Krishnamurthy ; P.R. Mukund. Institute of Electrical and Electronics Engineers Inc., 2002. pp. 433-437 (Proceedings of the Annual IEEE International ASIC Conference and Exhibit).
@inproceedings{4c063d032ef94052812f70cdb30d7298,
title = "Characterizing dynamic and leakage power behavior in flip-flops",
abstract = "This paper presents a detailed analysis of power consumption in a variety of flip-flop designs including scannable latches. The analysis was performed by implementing and simulating the different designs using 70 nm, IV CMOS technology. First, we perform a detailed characterization of the dynamic power consumption due to output transitions and that due to clock and data transitions when there is no output transition. Further, we also characterize the leakage behavior of each of the flip-flop designs and specifically, characterize the input dependence of leakage.",
author = "R. Ramanarayanan and Vijaykrishnan Narayanan and Irwin, {Mary Jane}",
year = "2002",
month = "1",
day = "1",
doi = "10.1109/ASIC.2002.1158098",
language = "English (US)",
series = "Proceedings of the Annual IEEE International ASIC Conference and Exhibit",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "433--437",
editor = "John Chickanosky and Krishnamurthy, {Ram K.} and P.R. Mukund",
booktitle = "Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002",
address = "United States",

}

Ramanarayanan, R, Narayanan, V & Irwin, MJ 2002, Characterizing dynamic and leakage power behavior in flip-flops. in J Chickanosky, RK Krishnamurthy & PR Mukund (eds), Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002., 1158098, Proceedings of the Annual IEEE International ASIC Conference and Exhibit, vol. 2002-January, Institute of Electrical and Electronics Engineers Inc., pp. 433-437, 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002, Rochester, United States, 9/25/02. https://doi.org/10.1109/ASIC.2002.1158098

Characterizing dynamic and leakage power behavior in flip-flops. / Ramanarayanan, R.; Narayanan, Vijaykrishnan; Irwin, Mary Jane.

Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. ed. / John Chickanosky; Ram K. Krishnamurthy; P.R. Mukund. Institute of Electrical and Electronics Engineers Inc., 2002. p. 433-437 1158098 (Proceedings of the Annual IEEE International ASIC Conference and Exhibit; Vol. 2002-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Characterizing dynamic and leakage power behavior in flip-flops

AU - Ramanarayanan, R.

AU - Narayanan, Vijaykrishnan

AU - Irwin, Mary Jane

PY - 2002/1/1

Y1 - 2002/1/1

N2 - This paper presents a detailed analysis of power consumption in a variety of flip-flop designs including scannable latches. The analysis was performed by implementing and simulating the different designs using 70 nm, IV CMOS technology. First, we perform a detailed characterization of the dynamic power consumption due to output transitions and that due to clock and data transitions when there is no output transition. Further, we also characterize the leakage behavior of each of the flip-flop designs and specifically, characterize the input dependence of leakage.

AB - This paper presents a detailed analysis of power consumption in a variety of flip-flop designs including scannable latches. The analysis was performed by implementing and simulating the different designs using 70 nm, IV CMOS technology. First, we perform a detailed characterization of the dynamic power consumption due to output transitions and that due to clock and data transitions when there is no output transition. Further, we also characterize the leakage behavior of each of the flip-flop designs and specifically, characterize the input dependence of leakage.

UR - http://www.scopus.com/inward/record.url?scp=33847211913&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33847211913&partnerID=8YFLogxK

U2 - 10.1109/ASIC.2002.1158098

DO - 10.1109/ASIC.2002.1158098

M3 - Conference contribution

AN - SCOPUS:33847211913

T3 - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

SP - 433

EP - 437

BT - Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002

A2 - Chickanosky, John

A2 - Krishnamurthy, Ram K.

A2 - Mukund, P.R.

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Ramanarayanan R, Narayanan V, Irwin MJ. Characterizing dynamic and leakage power behavior in flip-flops. In Chickanosky J, Krishnamurthy RK, Mukund PR, editors, Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. Institute of Electrical and Electronics Engineers Inc. 2002. p. 433-437. 1158098. (Proceedings of the Annual IEEE International ASIC Conference and Exhibit). https://doi.org/10.1109/ASIC.2002.1158098