Degradation of metal-insulator-semiconductor (MIS) capacitors of gold/Parylene-C/Pentacene under constant voltage stress (CVS) was investigated to explore the electrical stability and reliability of Parylene C as a gate dielectric in flexible electronics. A stress voltage of fixed magnitude as high as 20 V, both negative and positive in polarity, was applied to each MIS capacitor at room temperature for a fixed duration as long as 10 s. The CVS effects on the capacitance-voltage curve-shift, the time-dependent leakage current and the time-dependent dielectric breakdown were measured and analyzed. CVS is observed to induce charge in Parylene-C and its interfaces with gold and Pentacene. The net induced charge is positive and negative for, respectively, negative and positive gate bias polarity during CVS. The magnitude of the charge accumulated following positive gate CVS is significantly higher than that following negative gate bias CVS in the range of 4 to 25 nC cm-2. In contrast, the leakage current during the negative gate stress is three orders of magnitude higher than that during the positive gate stress for the same bias stress magnitude. The charge buildup and leakage current are due to the trapping of electrons and holes near the Parylene-C/Pentacene interface as well as in the Parylene-C layer. Before the application of the CVS, a dielectric breakdown occurs at an electric field of 1.62 MV cm-1. After the application of the CVS, the breakdown voltage decreases and the density of the trapped charges increases as the stress voltage increases in magnitude, with the polarity of the trapped charges opposite to that of the stress voltage. The magnitude and direction of the capacitance-voltage curve-shift depend on the trapping and recombination of electrons and holes in the Parylene-C layer and in the proximity of the Parylene-C/Pentacene interface during CVS.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering