ChipPower: An architecture-level leakage simulator

Yuh Fang Tsai, Ananth Hegde Ankadi, N. Vijaykrishnan, Mary Jane Irwin, Theo Theocharides

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Scopus citations

Abstract

Leakage power is projected to be one of the major challenges in future technology generations. The temperature profile, process variation, and transistor count all have strong impact on the leakage power distribution of a processor. We have built a simulator to estimate the dynamic/leakage power for a VLIW architecture considering dynamic temperature feedback and process variation. The framework is based on architecture similar to the Intel Itanium IA64 and is extended to simulate its power when implemented in 65nm technology. Our experimental results show that leakage power will become more than 50% of the power budget in 65nm technology. Moreover, without including the process variation, the total leakage power will be underestimated by as much as 30%.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International SOC Conference
EditorsJ. Chickanosky, D. Ha, R. Auletta
Pages395-398
Number of pages4
StatePublished - Dec 1 2004
EventProceedings - IEEE International SOC Conference - Santa Clara, CA, United States
Duration: Sep 12 2004Sep 15 2004

Publication series

NameProceedings - IEEE International SOC Conference

Other

OtherProceedings - IEEE International SOC Conference
CountryUnited States
CitySanta Clara, CA
Period9/12/049/15/04

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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    Tsai, Y. F., Ankadi, A. H., Vijaykrishnan, N., Irwin, M. J., & Theocharides, T. (2004). ChipPower: An architecture-level leakage simulator. In J. Chickanosky, D. Ha, & R. Auletta (Eds.), Proceedings - IEEE International SOC Conference (pp. 395-398). [WB3.2] (Proceedings - IEEE International SOC Conference).