ChipPower

An architecture-level leakage simulator

Yuh Fang Tsai, Ananth Hegde Ankadi, Vijaykrishnan Narayanan, Mary Jane Irwin, Theo Theocharides

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Abstract

Leakage power is projected to be one of the major challenges in future technology generations. The temperature profile, process variation, and transistor count all have strong impact on the leakage power distribution of a processor. We have built a simulator to estimate the dynamic/leakage power for a VLIW architecture considering dynamic temperature feedback and process variation. The framework is based on architecture similar to the Intel Itanium IA64 and is extended to simulate its power when implemented in 65nm technology. Our experimental results show that leakage power will become more than 50% of the power budget in 65nm technology. Moreover, without including the process variation, the total leakage power will be underestimated by as much as 30%.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International SOC Conference
EditorsJ. Chickanosky, D. Ha, R. Auletta
Pages395-398
Number of pages4
StatePublished - 2004
EventProceedings - IEEE International SOC Conference - Santa Clara, CA, United States
Duration: Sep 12 2004Sep 15 2004

Other

OtherProceedings - IEEE International SOC Conference
CountryUnited States
CitySanta Clara, CA
Period9/12/049/15/04

Fingerprint

Simulators
Very long instruction word architecture
Transistors
Feedback
Temperature

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Tsai, Y. F., Ankadi, A. H., Narayanan, V., Irwin, M. J., & Theocharides, T. (2004). ChipPower: An architecture-level leakage simulator. In J. Chickanosky, D. Ha, & R. Auletta (Eds.), Proceedings - IEEE International SOC Conference (pp. 395-398). [WB3.2]
Tsai, Yuh Fang ; Ankadi, Ananth Hegde ; Narayanan, Vijaykrishnan ; Irwin, Mary Jane ; Theocharides, Theo. / ChipPower : An architecture-level leakage simulator. Proceedings - IEEE International SOC Conference. editor / J. Chickanosky ; D. Ha ; R. Auletta. 2004. pp. 395-398
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Tsai, YF, Ankadi, AH, Narayanan, V, Irwin, MJ & Theocharides, T 2004, ChipPower: An architecture-level leakage simulator. in J Chickanosky, D Ha & R Auletta (eds), Proceedings - IEEE International SOC Conference., WB3.2, pp. 395-398, Proceedings - IEEE International SOC Conference, Santa Clara, CA, United States, 9/12/04.

ChipPower : An architecture-level leakage simulator. / Tsai, Yuh Fang; Ankadi, Ananth Hegde; Narayanan, Vijaykrishnan; Irwin, Mary Jane; Theocharides, Theo.

Proceedings - IEEE International SOC Conference. ed. / J. Chickanosky; D. Ha; R. Auletta. 2004. p. 395-398 WB3.2.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Tsai YF, Ankadi AH, Narayanan V, Irwin MJ, Theocharides T. ChipPower: An architecture-level leakage simulator. In Chickanosky J, Ha D, Auletta R, editors, Proceedings - IEEE International SOC Conference. 2004. p. 395-398. WB3.2