Circuit design methodologies for test power reduction in nano-scaled technologies

Veena S. Chakravarthi, Swaroop Ghosh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Test power has emerged as an important design concern in nano-scaled technologies. The BIST circuitry for periodic self-test consumes significant power in hand-held electronic devices to increase battery lifetime. Reduced test power of a module allows parallel testing of multiple embedded cores in an IC. Peak and average power reduction during test contribute to enhanced reliability and improved yield. In this paper, we present circuit design methodologies to reduce test power in nano-scaled technologies. In addition to this advantage of reduced supply, testing concept is mentioned for initial testing which will give dual benefit of power and test time reduction.

Original languageEnglish (US)
Title of host publicationProceedings of International Conference on VLSI, Communication, Advanced Devices, Signals and Systems and Networking, VCASAN 2013
Pages139-149
Number of pages11
DOIs
StatePublished - Aug 12 2013
EventInternational Conference on VLSI, Communication, Advanced Devices, Signals and Systems and Networking, VCASAN 2013 - Bengaluru, Karnataka, India
Duration: Jul 17 2013Jul 19 2013

Publication series

NameLecture Notes in Electrical Engineering
Volume258 LNEE
ISSN (Print)1876-1100
ISSN (Electronic)1876-1119

Other

OtherInternational Conference on VLSI, Communication, Advanced Devices, Signals and Systems and Networking, VCASAN 2013
CountryIndia
CityBengaluru, Karnataka
Period7/17/137/19/13

Fingerprint

Nanotechnology
Networks (circuits)
Testing
Built-in self test

All Science Journal Classification (ASJC) codes

  • Industrial and Manufacturing Engineering

Cite this

Chakravarthi, V. S., & Ghosh, S. (2013). Circuit design methodologies for test power reduction in nano-scaled technologies. In Proceedings of International Conference on VLSI, Communication, Advanced Devices, Signals and Systems and Networking, VCASAN 2013 (pp. 139-149). (Lecture Notes in Electrical Engineering; Vol. 258 LNEE). https://doi.org/10.1007/978-81-322-1524-0_20
Chakravarthi, Veena S. ; Ghosh, Swaroop. / Circuit design methodologies for test power reduction in nano-scaled technologies. Proceedings of International Conference on VLSI, Communication, Advanced Devices, Signals and Systems and Networking, VCASAN 2013. 2013. pp. 139-149 (Lecture Notes in Electrical Engineering).
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Chakravarthi, VS & Ghosh, S 2013, Circuit design methodologies for test power reduction in nano-scaled technologies. in Proceedings of International Conference on VLSI, Communication, Advanced Devices, Signals and Systems and Networking, VCASAN 2013. Lecture Notes in Electrical Engineering, vol. 258 LNEE, pp. 139-149, International Conference on VLSI, Communication, Advanced Devices, Signals and Systems and Networking, VCASAN 2013, Bengaluru, Karnataka, India, 7/17/13. https://doi.org/10.1007/978-81-322-1524-0_20

Circuit design methodologies for test power reduction in nano-scaled technologies. / Chakravarthi, Veena S.; Ghosh, Swaroop.

Proceedings of International Conference on VLSI, Communication, Advanced Devices, Signals and Systems and Networking, VCASAN 2013. 2013. p. 139-149 (Lecture Notes in Electrical Engineering; Vol. 258 LNEE).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Chakravarthi VS, Ghosh S. Circuit design methodologies for test power reduction in nano-scaled technologies. In Proceedings of International Conference on VLSI, Communication, Advanced Devices, Signals and Systems and Networking, VCASAN 2013. 2013. p. 139-149. (Lecture Notes in Electrical Engineering). https://doi.org/10.1007/978-81-322-1524-0_20