Circuit-level impact of a-Si:H thin-film-transistor degradation effects

David R. Allee, Lawrence T. Clark, Bryan D. Vogt, Rahul Shringarpure, Sameer M. Venugopal, Shrinivas Gopalan Uppili, Korhan Kaftanoglu, Hemanth Shivalingaiah, Zi P. Li, J. J.Ravindra Fernando, Edward J. Bawolek, Shawn M. O'Rourke

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Abstract

This paper reviews amorphous silicon thin-film-transistor (TFT) degradation with electrical stress, examining the implications for various types of circuitry. Experimental measurements on active-matrix backplanes, integrated a-Si:H column drivers, and a-Si:H digital circuitry are performed. Circuit modeling that enables the prediction of complex-circuit degradation is described. The similarity of degradation in amorphous silicon to negative bias temperature instability in crystalline PMOS FETs is discussed as well as approaches in reducing the TFT degradation effects. Experimental electrical-stress-induced degradation results in controlled humidity environments are also presented.

Original languageEnglish (US)
Pages (from-to)1166-1176
Number of pages11
JournalIEEE Transactions on Electron Devices
Volume56
Issue number6
DOIs
StatePublished - Jun 17 2009

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Allee, D. R., Clark, L. T., Vogt, B. D., Shringarpure, R., Venugopal, S. M., Uppili, S. G., Kaftanoglu, K., Shivalingaiah, H., Li, Z. P., Fernando, J. J. R., Bawolek, E. J., & O'Rourke, S. M. (2009). Circuit-level impact of a-Si:H thin-film-transistor degradation effects. IEEE Transactions on Electron Devices, 56(6), 1166-1176. https://doi.org/10.1109/TED.2009.2019387