Three circuits are described as an initial step toward implementing an analog VLSI-based backpropagation neural network. One of these circuits is the connectivity matrix for a fully connected five-input perceptron. The second is a summer circuit that immediately computes total backpropagated error. The third is a triggerable processor that optimizes a given synaptic weight with respect to backpropagated error. Performed in hardware, the operations performed by these circuits will take place in parallel, and in real time. As such, they will allow the neural network to converge at a higher speed than software-based counterparts. The circuitry for this network has been implemented in 2-micron CMOS technology, and will form the bases for truly parallel and simultaneous standalone neural networks that operate in real time without intervention from digital computers.