Clock power issues in system-on-a-chip designs

R. Y. Chen, N. Vijaykrishnan, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

20 Scopus citations

Abstract

The paper investigates some issues on clock power consumption in system-on-a-chip (SoC) designs. Since clock power consumption is often the largest part of total chip power research in this area becomes urgent. In a SoC the clock depends not only on clock distribution wiring, clock driver sizing and the capability to disable part of the clock network, but also on circuit design style, architectural choice and the clock rate of the IP blocks. The different IP blocks may require that multiple-frequency clocks are distributed on the chip. Our research provides a clock power model for SoC that takes into account these various factors. The impact of architectural, design, and logic style on clock power is studied using adder and register designs. In research, such characterizing information on SoC designs will be used in designing the clock network and estimating its power dissipation.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE Computer Society Workshop on VLSI 1999
Subtitle of host publicationSystem Design: Towards System-on-a-Chip Paradigm, VLSI 1999
EditorsRobert Brodersen, Asim Smailagic, Hugo De Man
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages48-53
Number of pages6
ISBN (Electronic)0769501524, 9780769501529
DOIs
StatePublished - Jan 1 1999
Event1999 IEEE Computer Society Workshop on VLSI, VLSI 1999 - Orlando, United States
Duration: Apr 8 1999Apr 9 1999

Publication series

NameProceedings - IEEE Computer Society Workshop on VLSI 1999: System Design: Towards System-on-a-Chip Paradigm, VLSI 1999

Other

Other1999 IEEE Computer Society Workshop on VLSI, VLSI 1999
CountryUnited States
CityOrlando
Period4/8/994/9/99

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Software

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