Clocked, static circuit technique for building efficient high frequency pipelines

Eric Gayles, Kevin Acken, Robert M. Owens, Mary Jane Irwin

Research output: Contribution to journalConference article

1 Citation (Scopus)

Abstract

This paper presents a CMOS circuit methodology for designing pipeline stages which are both faster than comparable domino based stages and that also have increased functional capability. The basic gates offer considerably faster switching speeds than domino, which also eliminating the feedback and buffering circuitry required by domino gates for reliable operation. In addition to faster gates, the dual-rail nature of the proposed circuit technique provides greater logic functionality per gate. This results in a reduction of the number of gate delays required for implementing complex functions of high fan-in. Several benchmark circuits were simulated in a 0.5 μm, 3.3 V CMOS process. The results show that the proposed circuit technique provides significant speed improvement over domino.

Original languageEnglish (US)
Pages (from-to)182-187
Number of pages6
JournalProceedings of the IEEE Great Lakes Symposium on VLSI
StatePublished - Jan 1 1997
EventProceedings of the 1997 7th Great Lakes Symposium on VLSI - Urbana-Champaign, IL, USA
Duration: Mar 13 1997Mar 15 1997

Fingerprint

Pipelines
Networks (circuits)
Rails
Feedback

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Gayles, Eric ; Acken, Kevin ; Owens, Robert M. ; Irwin, Mary Jane. / Clocked, static circuit technique for building efficient high frequency pipelines. In: Proceedings of the IEEE Great Lakes Symposium on VLSI. 1997 ; pp. 182-187.
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Clocked, static circuit technique for building efficient high frequency pipelines. / Gayles, Eric; Acken, Kevin; Owens, Robert M.; Irwin, Mary Jane.

In: Proceedings of the IEEE Great Lakes Symposium on VLSI, 01.01.1997, p. 182-187.

Research output: Contribution to journalConference article

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