Combined multiplication and sum-of-squares units

Michael J. Schulte, Louis Marquette, Shankar Krithivasan, E. George Walters, John Glossner

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

Multiplication and squaring are important operations in digital signal processing and multimedia applications. We present designs for units that implement either multiplication, A×B, or sum-of-squares computations, A2+B2, based on an input control signal. Compared to conventional parallel multipliers, these units have a modest increase in area and delay, but allow either multiplication or sum-of-squares computations to be performed. Combined multiplication and sum-of-squares units for unsigned and two's complement operands are presented, along with integrated designs that can operate on either unsigned or two's complement operands. The designs can also be extended to work with a third accumulator operand to compute either Z+A×B or Z+A2+B2/. Synthesis results indicate that a combined multiplication and sum-of-squares unit for 32-bit two's complement operands can be implemented with roughly 15% more area and nearly the same worst case delay as a conventional 32-bit two's complement multiplier.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2003
EditorsEd Deprettere, Shuvra Bhattacharyya, Lothar Thiele, Joseph Cavallaro, Alain Darte
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages204-214
Number of pages11
ISBN (Electronic)076951992X
DOIs
StatePublished - Jan 1 2003
EventIEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2003 - The Hague, Netherlands
Duration: Jun 24 2003Jun 26 2003

Publication series

NameProceedings of the International Conference on Application-Specific Systems, Architectures and Processors
Volume2003-January
ISSN (Print)1063-6862

Other

OtherIEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2003
CountryNetherlands
CityThe Hague
Period6/24/036/26/03

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Computer Networks and Communications

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  • Cite this

    Schulte, M. J., Marquette, L., Krithivasan, S., Walters, E. G., & Glossner, J. (2003). Combined multiplication and sum-of-squares units. In E. Deprettere, S. Bhattacharyya, L. Thiele, J. Cavallaro, & A. Darte (Eds.), Proceedings - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2003 (pp. 204-214). [1212844] (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors; Vol. 2003-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASAP.2003.1212844