Combined unsigned and two's complement hybrid squarers

E. George Walters, Jason Schlessman, Michael J. Schulte

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

Designs for high-speed combined squarers, capable of operating on either unsigned or two's complement numbers, are presented. High speed is achieved in part by using a modestly sized ROM table to generate the less significant bits of the square, and combinational logic to generate the more significant bits. These squarers have a shorter carry propagate chain in the final adder and a smaller amount of combinational logic than previous hybrid designs. Area and delay estimates indicate that the combined hybrid squarers presented in this paper have between 28% and 64% percent less area and between 9% and 15% percent less delay than previous unsigned hybrid squarers for 32-bit operands.

Original languageEnglish (US)
Pages (from-to)861-866
Number of pages6
JournalConference Record of the Asilomar Conference on Signals, Systems and Computers
Volume1
DOIs
StatePublished - Jan 1 2001

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All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Networks and Communications

Cite this

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Combined unsigned and two's complement hybrid squarers. / Walters, E. George; Schlessman, Jason; Schulte, Michael J.

In: Conference Record of the Asilomar Conference on Signals, Systems and Computers, Vol. 1, 01.01.2001, p. 861-866.

Research output: Contribution to journalArticle

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