Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

Mamidala Jagadesh Kumar, Sumeet Kumar Gupta, Vivek Venkataraman

Research output: Contribution to journalArticle

36 Citations (Scopus)

Abstract

A compact model for the effect of the parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric silicon-on-insulator MOSFETs is developed. The authors' model includes the effects of the gate-dielectric permittivity, spacer oxide permittivity, spacer width, gate length, and the width of an MOS structure. A simple expression for the parasitic internal fringe capacitance from the bottom edge of the gate electrode is obtained and the charges induced in the source and drain regions due to this capacitance are considered. The authors demonstrate an increase in the surface potential along the channel due to these charges, resulting in a decrease in the threshold voltage with an increase in the gate-dielectric permittivity. The accuracy of the results obtained using the authors' analytical model is verified using two-dimensional device simulations.

Original languageEnglish (US)
Pages (from-to)706-711
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume53
Issue number4
DOIs
StatePublished - Apr 1 2006

Fingerprint

Gate dielectrics
SOI (semiconductors)
Threshold voltage
threshold voltage
Permittivity
Capacitance
field effect transistors
capacitance
permittivity
spacers
Surface potential
Silicon
Oxides
Analytical models
Electrodes
insulators
electrodes
oxides
silicon
simulation

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Physics and Astronomy (miscellaneous)

Cite this

@article{bb45ef3844a14c9abf5c312fe48638a4,
title = "Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs",
abstract = "A compact model for the effect of the parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric silicon-on-insulator MOSFETs is developed. The authors' model includes the effects of the gate-dielectric permittivity, spacer oxide permittivity, spacer width, gate length, and the width of an MOS structure. A simple expression for the parasitic internal fringe capacitance from the bottom edge of the gate electrode is obtained and the charges induced in the source and drain regions due to this capacitance are considered. The authors demonstrate an increase in the surface potential along the channel due to these charges, resulting in a decrease in the threshold voltage with an increase in the gate-dielectric permittivity. The accuracy of the results obtained using the authors' analytical model is verified using two-dimensional device simulations.",
author = "Kumar, {Mamidala Jagadesh} and Gupta, {Sumeet Kumar} and Vivek Venkataraman",
year = "2006",
month = "4",
day = "1",
doi = "10.1109/TED.2006.870424",
language = "English (US)",
volume = "53",
pages = "706--711",
journal = "IEEE Transactions on Electron Devices",
issn = "0018-9383",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "4",

}

Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs. / Kumar, Mamidala Jagadesh; Gupta, Sumeet Kumar; Venkataraman, Vivek.

In: IEEE Transactions on Electron Devices, Vol. 53, No. 4, 01.04.2006, p. 706-711.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

AU - Kumar, Mamidala Jagadesh

AU - Gupta, Sumeet Kumar

AU - Venkataraman, Vivek

PY - 2006/4/1

Y1 - 2006/4/1

N2 - A compact model for the effect of the parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric silicon-on-insulator MOSFETs is developed. The authors' model includes the effects of the gate-dielectric permittivity, spacer oxide permittivity, spacer width, gate length, and the width of an MOS structure. A simple expression for the parasitic internal fringe capacitance from the bottom edge of the gate electrode is obtained and the charges induced in the source and drain regions due to this capacitance are considered. The authors demonstrate an increase in the surface potential along the channel due to these charges, resulting in a decrease in the threshold voltage with an increase in the gate-dielectric permittivity. The accuracy of the results obtained using the authors' analytical model is verified using two-dimensional device simulations.

AB - A compact model for the effect of the parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric silicon-on-insulator MOSFETs is developed. The authors' model includes the effects of the gate-dielectric permittivity, spacer oxide permittivity, spacer width, gate length, and the width of an MOS structure. A simple expression for the parasitic internal fringe capacitance from the bottom edge of the gate electrode is obtained and the charges induced in the source and drain regions due to this capacitance are considered. The authors demonstrate an increase in the surface potential along the channel due to these charges, resulting in a decrease in the threshold voltage with an increase in the gate-dielectric permittivity. The accuracy of the results obtained using the authors' analytical model is verified using two-dimensional device simulations.

UR - http://www.scopus.com/inward/record.url?scp=33645740144&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33645740144&partnerID=8YFLogxK

U2 - 10.1109/TED.2006.870424

DO - 10.1109/TED.2006.870424

M3 - Article

AN - SCOPUS:33645740144

VL - 53

SP - 706

EP - 711

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

SN - 0018-9383

IS - 4

ER -