Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

Mamidala Jagadesh Kumar, Sumeet Kumar Gupta, Vivek Venkataraman

Research output: Contribution to journalArticle

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Abstract

A compact model for the effect of the parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric silicon-on-insulator MOSFETs is developed. The authors' model includes the effects of the gate-dielectric permittivity, spacer oxide permittivity, spacer width, gate length, and the width of an MOS structure. A simple expression for the parasitic internal fringe capacitance from the bottom edge of the gate electrode is obtained and the charges induced in the source and drain regions due to this capacitance are considered. The authors demonstrate an increase in the surface potential along the channel due to these charges, resulting in a decrease in the threshold voltage with an increase in the gate-dielectric permittivity. The accuracy of the results obtained using the authors' analytical model is verified using two-dimensional device simulations.

Original languageEnglish (US)
Pages (from-to)706-711
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume53
Issue number4
DOIs
Publication statusPublished - Apr 1 2006

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All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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