This paper presents a circuit perspective on complementary metal oxide semiconductor (CMOS) limits by analyzing a standard CMOS inverter driving a capacitive load at ultralow supply voltages. While the behavior of an inverter is well understood and modeled in the superthreshold region and for sufficiently high supply voltages in the subthreshold region, the analysis at ultralow supply voltages is different. In this region of operation, the voltage levels corresponding to logic "1" and logic "0" are not Vdd and Gnd, respectively. We model the incomplete voltage swing and show that the minimum supply voltage for a CMOS inverter (with pull-up and pull-down devices as ideal conventional metal oxide semiconductor field effect transistors) is, indeed, 2kT/q ln 2. The novelty of this approach lies in the fact that it gives an explicit mathematical relationship between the supply voltage and a measure of distinguishability of the binary states defined in terms of the expected voltage swing. The analysis shows that the minimum supply voltage corresponds to the state when the two states become completely indistinguishable. Further, we obtain a relationship between the switching energy and robustness of CMOS inverters and interconnects, valid for the entire range of supply voltages. This analysis also shows that a minimum supply voltage of 2kT/q ln 2 may not correspond to the fundamental energy dissipation of kT ln 2.
All Science Journal Classification (ASJC) codes
- Physics and Astronomy(all)