Comparative study of power efficient SRAM designs

Jeyran Hezavei, N. Vijaykrishnan, M. J. Irwin

Research output: Contribution to journalConference articlepeer-review

9 Scopus citations

Abstract

This paper investigates the effectiveness of combination of different low power SRAM circuit design techniques. The divided bit line (DBL), pulsed word line (PWL) and isolated bit line (IBL) strategies have been implemented in a various size SRAM designs and evaluated using 0.35 Micron technology and 3.3 V VDD at 100 MHz frequency. Different decoder structures have been investigated for their power efficiency as well. It is observed that the power reduces by 29%, 32% and 52% over an unoptimized SRAM design when (PWL+IBL), (PWL+DBL) and (PWL+IBL+DBL) are implemented in a 256*2 size SRAM respectively.

Original languageEnglish (US)
Pages (from-to)117-122
Number of pages6
JournalProceedings of the IEEE Great Lakes Symposium on VLSI
StatePublished - Jan 1 2000
EventGLSVLSI 2000: 10th Great Lakes Symposium on VLSI - Chicago, IL, USA
Duration: Mar 2 2000Mar 4 2000

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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