Comparing energy, area, delay tradeoffs in going vertical with CMOS and asymmetric HTFETs

Moon Seok Kim, William Cane-Wissing, Jack Sampson, Suman Datta, Vijaykrishnan Narayanan, Sumeet K. Gupta

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

Vertical transistors are one of the promising alternatives to standard lateral device structures in future technologies due to benefits in terms of reduced footprint and feasibility of fabrication of hetero junction structures. While such device-level benefits have been widely explored, the circuit and layout-level implications of vertical transistors require further analysis. In this work, we carry out a systematic layout and circuit analysis for 20nm vertical transistors, namely symmetrical vertical MOSFET and asymmetrical hetero junction tunnel FET (HTFET), and present a detailed comparison with 20nm Fin FETs. Our analysis clearly outlines the differences from the perspective of layouts and the performance/power of standard cells. The absence of width quantization in vertical FETs and steep switching characteristics in HTFETs result in larger drive strengths compared to Fin FETs. However, for high fan-in cells, vertical transistors show area overheads due to infeasibility of contact sharing in parallel and series transistors. For each type of device, we synthesized a 32-bit carry look ahead adder and compared energy, delay and area, taking into account layout differences due to the device structures. Our analysis shows that in spite of area overhead for some cells, high drive-strength in HTFET cells brings advantages in both area and energy over both Fin FETs and vertical MOSFETs at VDD < 0.6V.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2015
PublisherIEEE Computer Society
Pages303-308
Number of pages6
ISBN (Electronic)9781479987184
DOIs
Publication statusPublished - Oct 27 2015
EventIEEE Computer Society Annual Symposium on VLSI, ISVLSI 2015 - Montpellier, France
Duration: Jul 8 2015Jul 10 2015

Publication series

NameProceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume07-10-July-2015
ISSN (Print)2159-3469
ISSN (Electronic)2159-3477

Other

OtherIEEE Computer Society Annual Symposium on VLSI, ISVLSI 2015
CountryFrance
CityMontpellier
Period7/8/157/10/15

    Fingerprint

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Kim, M. S., Cane-Wissing, W., Sampson, J., Datta, S., Narayanan, V., & Gupta, S. K. (2015). Comparing energy, area, delay tradeoffs in going vertical with CMOS and asymmetric HTFETs. In Proceedings - IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2015 (pp. 303-308). [7309584] (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 07-10-July-2015). IEEE Computer Society. https://doi.org/10.1109/ISVLSI.2015.82