A standard method of high-speed digital channel simulation involves dividing the channel into discrete parts and analyzing each part independently to determine its individual S-parameters. These S-parameters are then combined or concatenated to determine the overall channel performance. Analyzed here is a portion of such a channel composed of a high-speed connector and it's footprint on a printed circuit board. For this structure, the paper compares the concatenation method to a single full-wave simulation of the entire structure. The first method is evaluated to determine its upper frequency limit thus showing when it is appropriate to use it over full-wave analysis, which is typically more complex and time consuming. Additionally, some structures that are not accounted for when using the concatenation method are investigated.