Comparison of two digit serial VLSI adders

Mary Jane Irwin, Robert Michael Owens

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

The VLSI design of two digit serial adders, one which processes operand digits and produces online result digits least-significant digit first, and one which processes operands and produces online result digits most-significant digit first, is presented. They are compared with respect to number of gates, interconnect lines, layout area, and digit and operand add time. An optimal gate level description suitable for static CMOS implementation for one of the adders is given. This gate-level description can be input to a layout tool to automatically produce the CMOS gate matrix layout of the description. Finally, word-parallel adders built out of the two digit serial adders are discussed and compared.

Original languageEnglish (US)
Title of host publication1988 IEEE Int Conf Comput Des VLSI Comput Process ICCD 88 Proc
PublisherPubl by IEEE
Pages227-229
Number of pages3
ISBN (Print)0818608722
StatePublished - Dec 1 1988

Publication series

Name1988 IEEE Int Conf Comput Des VLSI Comput Process ICCD 88 Proc

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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    Irwin, M. J., & Owens, R. M. (1988). Comparison of two digit serial VLSI adders. In 1988 IEEE Int Conf Comput Des VLSI Comput Process ICCD 88 Proc (pp. 227-229). (1988 IEEE Int Conf Comput Des VLSI Comput Process ICCD 88 Proc). Publ by IEEE.