The VLSI design of two digit serial adders, one which processes operand digits and produces online result digits least-significant digit first, and one which processes operands and produces online result digits most-significant digit first, is presented. They are compared with respect to number of gates, interconnect lines, layout area, and digit and operand add time. An optimal gate level description suitable for static CMOS implementation for one of the adders is given. This gate-level description can be input to a layout tool to automatically produce the CMOS gate matrix layout of the description. Finally, word-parallel adders built out of the two digit serial adders are discussed and compared.