Compiler-directed instruction cache leakage optimization

W. Zhang, J. S. Hu, V. Degalahal, M. Kandemir, N. Vijaykrishnan, M. J. Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

53 Citations (Scopus)

Abstract

Excessive power consumption is widely considered as a major impediment to designing future microprocessors. With the continued scaling down of threshold voltages, the power consumed due to leaky memory cells in on-chip caches will constitute a significant portion of the processor's power budget. This work focuses on reducing the leakage energy consumed in the instruction cache using a compiler-directed approach. We present and analyze two compiler-based strategies termed as conservative and optimistic. The conservative approach does not put a cache line into a low leakage mode until it is certain that the current instruction in it is dead. On the other hand, the optimistic approach places a cache line in low leakage mode if it detects that the next access to the instruction will occur only after a long gap. We evaluate different optimization alternatives by combining the compiler strategies with state-preserving and state-destroying leakage control mechanisms.

Original languageEnglish (US)
Title of host publicationProceedings - 35th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2002
PublisherIEEE Computer Society
Pages208-218
Number of pages11
ISBN (Electronic)0769518591
DOIs
StatePublished - Jan 1 2002
Event35th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2002 - Istanbul, Turkey
Duration: Nov 18 2002Nov 22 2002

Publication series

NameProceedings of the Annual International Symposium on Microarchitecture, MICRO
Volume2002-January
ISSN (Print)1072-4451

Other

Other35th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2002
CountryTurkey
CityIstanbul
Period11/18/0211/22/02

Fingerprint

Threshold voltage
Microprocessor chips
Electric power utilization
Data storage equipment

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Cite this

Zhang, W., Hu, J. S., Degalahal, V., Kandemir, M., Vijaykrishnan, N., & Irwin, M. J. (2002). Compiler-directed instruction cache leakage optimization. In Proceedings - 35th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2002 (pp. 208-218). [1176251] (Proceedings of the Annual International Symposium on Microarchitecture, MICRO; Vol. 2002-January). IEEE Computer Society. https://doi.org/10.1109/MICRO.2002.1176251
Zhang, W. ; Hu, J. S. ; Degalahal, V. ; Kandemir, M. ; Vijaykrishnan, N. ; Irwin, M. J. / Compiler-directed instruction cache leakage optimization. Proceedings - 35th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2002. IEEE Computer Society, 2002. pp. 208-218 (Proceedings of the Annual International Symposium on Microarchitecture, MICRO).
@inproceedings{150a21c98a6144a98aa9a5b6d30c8e68,
title = "Compiler-directed instruction cache leakage optimization",
abstract = "Excessive power consumption is widely considered as a major impediment to designing future microprocessors. With the continued scaling down of threshold voltages, the power consumed due to leaky memory cells in on-chip caches will constitute a significant portion of the processor's power budget. This work focuses on reducing the leakage energy consumed in the instruction cache using a compiler-directed approach. We present and analyze two compiler-based strategies termed as conservative and optimistic. The conservative approach does not put a cache line into a low leakage mode until it is certain that the current instruction in it is dead. On the other hand, the optimistic approach places a cache line in low leakage mode if it detects that the next access to the instruction will occur only after a long gap. We evaluate different optimization alternatives by combining the compiler strategies with state-preserving and state-destroying leakage control mechanisms.",
author = "W. Zhang and Hu, {J. S.} and V. Degalahal and M. Kandemir and N. Vijaykrishnan and Irwin, {M. J.}",
year = "2002",
month = "1",
day = "1",
doi = "10.1109/MICRO.2002.1176251",
language = "English (US)",
series = "Proceedings of the Annual International Symposium on Microarchitecture, MICRO",
publisher = "IEEE Computer Society",
pages = "208--218",
booktitle = "Proceedings - 35th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2002",
address = "United States",

}

Zhang, W, Hu, JS, Degalahal, V, Kandemir, M, Vijaykrishnan, N & Irwin, MJ 2002, Compiler-directed instruction cache leakage optimization. in Proceedings - 35th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2002., 1176251, Proceedings of the Annual International Symposium on Microarchitecture, MICRO, vol. 2002-January, IEEE Computer Society, pp. 208-218, 35th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2002, Istanbul, Turkey, 11/18/02. https://doi.org/10.1109/MICRO.2002.1176251

Compiler-directed instruction cache leakage optimization. / Zhang, W.; Hu, J. S.; Degalahal, V.; Kandemir, M.; Vijaykrishnan, N.; Irwin, M. J.

Proceedings - 35th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2002. IEEE Computer Society, 2002. p. 208-218 1176251 (Proceedings of the Annual International Symposium on Microarchitecture, MICRO; Vol. 2002-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Compiler-directed instruction cache leakage optimization

AU - Zhang, W.

AU - Hu, J. S.

AU - Degalahal, V.

AU - Kandemir, M.

AU - Vijaykrishnan, N.

AU - Irwin, M. J.

PY - 2002/1/1

Y1 - 2002/1/1

N2 - Excessive power consumption is widely considered as a major impediment to designing future microprocessors. With the continued scaling down of threshold voltages, the power consumed due to leaky memory cells in on-chip caches will constitute a significant portion of the processor's power budget. This work focuses on reducing the leakage energy consumed in the instruction cache using a compiler-directed approach. We present and analyze two compiler-based strategies termed as conservative and optimistic. The conservative approach does not put a cache line into a low leakage mode until it is certain that the current instruction in it is dead. On the other hand, the optimistic approach places a cache line in low leakage mode if it detects that the next access to the instruction will occur only after a long gap. We evaluate different optimization alternatives by combining the compiler strategies with state-preserving and state-destroying leakage control mechanisms.

AB - Excessive power consumption is widely considered as a major impediment to designing future microprocessors. With the continued scaling down of threshold voltages, the power consumed due to leaky memory cells in on-chip caches will constitute a significant portion of the processor's power budget. This work focuses on reducing the leakage energy consumed in the instruction cache using a compiler-directed approach. We present and analyze two compiler-based strategies termed as conservative and optimistic. The conservative approach does not put a cache line into a low leakage mode until it is certain that the current instruction in it is dead. On the other hand, the optimistic approach places a cache line in low leakage mode if it detects that the next access to the instruction will occur only after a long gap. We evaluate different optimization alternatives by combining the compiler strategies with state-preserving and state-destroying leakage control mechanisms.

UR - http://www.scopus.com/inward/record.url?scp=84948993747&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84948993747&partnerID=8YFLogxK

U2 - 10.1109/MICRO.2002.1176251

DO - 10.1109/MICRO.2002.1176251

M3 - Conference contribution

AN - SCOPUS:84948993747

T3 - Proceedings of the Annual International Symposium on Microarchitecture, MICRO

SP - 208

EP - 218

BT - Proceedings - 35th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2002

PB - IEEE Computer Society

ER -

Zhang W, Hu JS, Degalahal V, Kandemir M, Vijaykrishnan N, Irwin MJ. Compiler-directed instruction cache leakage optimization. In Proceedings - 35th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2002. IEEE Computer Society. 2002. p. 208-218. 1176251. (Proceedings of the Annual International Symposium on Microarchitecture, MICRO). https://doi.org/10.1109/MICRO.2002.1176251