Compiler-directed physical address generation for reducing dTLB power

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

Address translation using the Translation Lookaside Buffer (TLB) consumes as much as 16% of the chip power on some processors because of its high associativity and access frequency. While prior work has looked into optimizing this structure at the circuit and architectural levels, this paper takes a different approach of optimizing its power by reducing the number of data TLB (dTLB) lookups for data references. The main idea is to keep translations in a set of translation registers, and intelligently use them in software to directly generate the physical addresses without going through the dTLB. The software has to work within the confines of the translation registers provided by the hardware, and has to maximize the reuse of such translations to be effective. We propose strategies and code transformations for achieving this in array-based and pointer-based codes, looking to optimize data accesses. Results with a suite of Spec95 array-based and pointer-based codes show dTLB energy savings of up to 73% and 88%, respectively, compared to directly using the dTLB for all references. Despite the small increase in instructions executed with our mechanisms, the approach can in fact provide performance benefits in certain cases.

Original languageEnglish (US)
Title of host publication2004 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS
Pages161-168
Number of pages8
DOIs
StatePublished - 2004
Event2004 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS - Austin, TX., United States
Duration: Mar 10 2004Mar 12 2004

Other

Other2004 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS
CountryUnited States
CityAustin, TX.
Period3/10/043/12/04

Fingerprint

Physical addresses
Energy conservation
Hardware
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Kadayif, I., Nath, P., Kandemir, M., & Sivasubramaniam, A. (2004). Compiler-directed physical address generation for reducing dTLB power. In 2004 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS (pp. 161-168) https://doi.org/10.1109/ISPASS.2004.1291368
Kadayif, I. ; Nath, P. ; Kandemir, Mahmut ; Sivasubramaniam, Anand. / Compiler-directed physical address generation for reducing dTLB power. 2004 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS. 2004. pp. 161-168
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Kadayif, I, Nath, P, Kandemir, M & Sivasubramaniam, A 2004, Compiler-directed physical address generation for reducing dTLB power. in 2004 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS. pp. 161-168, 2004 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS, Austin, TX., United States, 3/10/04. https://doi.org/10.1109/ISPASS.2004.1291368

Compiler-directed physical address generation for reducing dTLB power. / Kadayif, I.; Nath, P.; Kandemir, Mahmut; Sivasubramaniam, Anand.

2004 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS. 2004. p. 161-168.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Kadayif I, Nath P, Kandemir M, Sivasubramaniam A. Compiler-directed physical address generation for reducing dTLB power. In 2004 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS. 2004. p. 161-168 https://doi.org/10.1109/ISPASS.2004.1291368