Compiler-Directed Proactive Power Management for Networks

Feihui Li, Guangyu Chen, Mahmut Kandemir, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

Increasing use of parallel computation platforms (both off-chip and on-chip) makes communication analysis and optimization an important target. While there have been numerous studies that target network performance of parallel architectures, the efforts that target network power consumption (in terms of both modeling and optimization) are relatively new. One of the common characteristics of most of the prior approaches to network power management is that they are hardware-based and reactive in the sense that they manage power consumption of the network as a response to observed message traffic. Consequently, they can miss important opportunities for saving power and can incur performance penalties due to inaccuracies in predicting future idle and active times of communication links. Motivated by this observation, this paper proposes a compiler-directed proactive approach to network power management for the class of loop-intensive applications running on small-sized networks used exclusively by a single embedded application at a time. As compared to hardware-based approaches, the proposed compiler-directed approach has two potential benefits. First, based on high-level communication analysis, it determines the points at which a given communication link is idle and can be turned off (i.e., powered down) to save power. Therefore, an idle link can be put in the low-power state without waiting for a certain period of time to make sure that the link has really become idle (as in the case of hardware schemes). Second, since the compiler can also determine the point at which a turned-off link will be needed in the future, it can pre-activate it (i.e., before it is actually needed) to eliminate the turn on (reactivation) performance penalty. Our simulations with seven array-intensive applications and an embedded on-chip network clearly show that the proposed compiler-directed approach is better than a hardware-based scheme from both power and performance perspectives.

Original languageEnglish (US)
Title of host publicationCASES 2005
Subtitle of host publicationInternational Conference on Compilers, Architecture, and Synthesis for Embedded Systems
PublisherAssociation for Computing Machinery (ACM)
Pages137-146
Number of pages10
ISBN (Print)159593149X, 9781595931498
DOIs
StatePublished - 2005
EventCASES 2005: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems - San Francisco, CA, United States
Duration: Sep 24 2005Sep 27 2005

Publication series

NameCASES 2005: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

Other

OtherCASES 2005: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems
CountryUnited States
CitySan Francisco, CA
Period9/24/059/27/05

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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