Compiler-directed selection of dynamic memory layouts

M. Kandemir, I. Kadayif

Research output: Contribution to conferencePaperpeer-review

12 Scopus citations

Abstract

Compiler technology is becoming a key component in the design of embedded systems, mostly due to increasing participation of software in the design process. Meeting system-level objectives usually requires flexible and retargetable compiler optimizations that can be ported across a wide variety of architectures. In particular, source-level compiler optimizations aiming at increasing locality of data accesses are expected to improve the quality of the generated code. Previous compiler-based approaches to improving locality have mainly focused on determining optimal memory layouts that remain in effect for the entire execution of an application. For large embedded codes, however, such static layouts may be insufficient to obtain acceptable performance. The selection of memory layouts that dynamically change over the course of a program's execution adds another dimension to data locality optimization. This paper presents a technique that can be used to automatically determine which layouts are most benefici al over specific regions of a program while taking into account the added overhead of dynamic (runtime) layout changes. The results obtained using two benchmark codes show that such a dynamic approach brings significant benefits over a static state-of-the-art technique.

Original languageEnglish (US)
Pages219-224
Number of pages6
DOIs
StatePublished - Jan 1 2001
Event9th International Symposium on Hardware/Software Codesign - Copenhagen, Denmark
Duration: Apr 25 2001Apr 27 2001

Other

Other9th International Symposium on Hardware/Software Codesign
CountryDenmark
CityCopenhagen
Period4/25/014/27/01

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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