Compiler-directed thermal management for VLIW functional units

Madhu Mutyam, Feihui Li, Vijaykrishnan Narayanan, Mahmut Kandemir, Mary Jane Irwin

Research output: Contribution to journalArticle

7 Citations (Scopus)

Abstract

As processors, memories, and other components of today's embedded systems are pushed to higher performance in more enclosed spaces, processor thermal management is quickly becoming a limiting design factor. While previous proposals mostly approached this thermal management problem from circuit and architecture angles, software can also play an important role in identifying and eliminating thermal hotspots as it is the main factor that shapes the order and frequency of accesses to different hardware components in the chip. This is particularly true for compiler-scheduled Very Long Instruction Word (VLIW) datapaths. In this paper, we focus on a compiler-based approach to make the thermal profile more balanced in the integer functional units of VLIW architectures. For balanced thermal behavior and peak temperature minimization, we propose techniques based on load balancing across the integer functional units with or without rotation of functional unit usage. As leakage power is exponentially dependent on temperature and temperature is dependent on total power (i.e., switching and leakage), in our techniques, we also consider leakage power optimization by IPC tuning (instructions issued per cycle). By taking a code that is already scheduled for maximum performance as input, our scheduling strategies modify this performance-oriented schedule for balanced thermal behavior with negligible performance degradation. We simulate our scheduling strategies using a framework that consists of the Trimaran infrastructure, a power model, and the HotSpot. Our experimental results using several benchmark programs reveal that the peak temperature can be reduced through compiler scheduling.

Original languageEnglish (US)
Pages (from-to)163-172
Number of pages10
JournalACM SIGPLAN Notices
Volume41
Issue number7
DOIs
StatePublished - Jul 1 2006

Fingerprint

Temperature control
Scheduling
Very long instruction word architecture
Temperature
Embedded systems
Resource allocation
Tuning
Hardware
Data storage equipment
Degradation
Hot Temperature
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design

Cite this

Mutyam, Madhu ; Li, Feihui ; Narayanan, Vijaykrishnan ; Kandemir, Mahmut ; Irwin, Mary Jane. / Compiler-directed thermal management for VLIW functional units. In: ACM SIGPLAN Notices. 2006 ; Vol. 41, No. 7. pp. 163-172.
@article{58da684fa6ee4cbd895380186a54741d,
title = "Compiler-directed thermal management for VLIW functional units",
abstract = "As processors, memories, and other components of today's embedded systems are pushed to higher performance in more enclosed spaces, processor thermal management is quickly becoming a limiting design factor. While previous proposals mostly approached this thermal management problem from circuit and architecture angles, software can also play an important role in identifying and eliminating thermal hotspots as it is the main factor that shapes the order and frequency of accesses to different hardware components in the chip. This is particularly true for compiler-scheduled Very Long Instruction Word (VLIW) datapaths. In this paper, we focus on a compiler-based approach to make the thermal profile more balanced in the integer functional units of VLIW architectures. For balanced thermal behavior and peak temperature minimization, we propose techniques based on load balancing across the integer functional units with or without rotation of functional unit usage. As leakage power is exponentially dependent on temperature and temperature is dependent on total power (i.e., switching and leakage), in our techniques, we also consider leakage power optimization by IPC tuning (instructions issued per cycle). By taking a code that is already scheduled for maximum performance as input, our scheduling strategies modify this performance-oriented schedule for balanced thermal behavior with negligible performance degradation. We simulate our scheduling strategies using a framework that consists of the Trimaran infrastructure, a power model, and the HotSpot. Our experimental results using several benchmark programs reveal that the peak temperature can be reduced through compiler scheduling.",
author = "Madhu Mutyam and Feihui Li and Vijaykrishnan Narayanan and Mahmut Kandemir and Irwin, {Mary Jane}",
year = "2006",
month = "7",
day = "1",
doi = "10.1145/1159974.1134674",
language = "English (US)",
volume = "41",
pages = "163--172",
journal = "ACM SIGPLAN Notices",
issn = "1523-2867",
publisher = "Association for Computing Machinery (ACM)",
number = "7",

}

Compiler-directed thermal management for VLIW functional units. / Mutyam, Madhu; Li, Feihui; Narayanan, Vijaykrishnan; Kandemir, Mahmut; Irwin, Mary Jane.

In: ACM SIGPLAN Notices, Vol. 41, No. 7, 01.07.2006, p. 163-172.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Compiler-directed thermal management for VLIW functional units

AU - Mutyam, Madhu

AU - Li, Feihui

AU - Narayanan, Vijaykrishnan

AU - Kandemir, Mahmut

AU - Irwin, Mary Jane

PY - 2006/7/1

Y1 - 2006/7/1

N2 - As processors, memories, and other components of today's embedded systems are pushed to higher performance in more enclosed spaces, processor thermal management is quickly becoming a limiting design factor. While previous proposals mostly approached this thermal management problem from circuit and architecture angles, software can also play an important role in identifying and eliminating thermal hotspots as it is the main factor that shapes the order and frequency of accesses to different hardware components in the chip. This is particularly true for compiler-scheduled Very Long Instruction Word (VLIW) datapaths. In this paper, we focus on a compiler-based approach to make the thermal profile more balanced in the integer functional units of VLIW architectures. For balanced thermal behavior and peak temperature minimization, we propose techniques based on load balancing across the integer functional units with or without rotation of functional unit usage. As leakage power is exponentially dependent on temperature and temperature is dependent on total power (i.e., switching and leakage), in our techniques, we also consider leakage power optimization by IPC tuning (instructions issued per cycle). By taking a code that is already scheduled for maximum performance as input, our scheduling strategies modify this performance-oriented schedule for balanced thermal behavior with negligible performance degradation. We simulate our scheduling strategies using a framework that consists of the Trimaran infrastructure, a power model, and the HotSpot. Our experimental results using several benchmark programs reveal that the peak temperature can be reduced through compiler scheduling.

AB - As processors, memories, and other components of today's embedded systems are pushed to higher performance in more enclosed spaces, processor thermal management is quickly becoming a limiting design factor. While previous proposals mostly approached this thermal management problem from circuit and architecture angles, software can also play an important role in identifying and eliminating thermal hotspots as it is the main factor that shapes the order and frequency of accesses to different hardware components in the chip. This is particularly true for compiler-scheduled Very Long Instruction Word (VLIW) datapaths. In this paper, we focus on a compiler-based approach to make the thermal profile more balanced in the integer functional units of VLIW architectures. For balanced thermal behavior and peak temperature minimization, we propose techniques based on load balancing across the integer functional units with or without rotation of functional unit usage. As leakage power is exponentially dependent on temperature and temperature is dependent on total power (i.e., switching and leakage), in our techniques, we also consider leakage power optimization by IPC tuning (instructions issued per cycle). By taking a code that is already scheduled for maximum performance as input, our scheduling strategies modify this performance-oriented schedule for balanced thermal behavior with negligible performance degradation. We simulate our scheduling strategies using a framework that consists of the Trimaran infrastructure, a power model, and the HotSpot. Our experimental results using several benchmark programs reveal that the peak temperature can be reduced through compiler scheduling.

UR - http://www.scopus.com/inward/record.url?scp=33749026682&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33749026682&partnerID=8YFLogxK

U2 - 10.1145/1159974.1134674

DO - 10.1145/1159974.1134674

M3 - Article

AN - SCOPUS:33749026682

VL - 41

SP - 163

EP - 172

JO - ACM SIGPLAN Notices

JF - ACM SIGPLAN Notices

SN - 1523-2867

IS - 7

ER -