Compiler Support for Optimizing Memory Bank-Level Parallelism

Wei Ding, Diana Guttman, Mahmut Kandemir

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Many prior compiler-based optimization schemes focused exclusively on cache data locality. However, cache locality is only one part of the overall performance of applications running on emerging multicores or many cores. For example, memory stalls could constitute a very large fraction of execution time even in cache-optimized codes, and one of the main reasons for this is lack of memory-level parallelism. Motivated by this, we propose a compiler-based Bank-Level Parallelism (BLP) optimization scheme that uses loop tile scheduling. More specifically, we first use Cache Miss Equations to predict where the last-level cache miss will happen in each tile, and then identify the set of memory banks that will be accessed in each tile. Using this information, two tile scheduling algorithms are proposed to maximize BLP, each targeting a different scenario. We further discuss how our compiler-based scheme can be enhanced to consider memory controller-level parallelism and row-buffer locality. Our experimental evaluation using 11 multithreaded applications shows that the proposed BLP optimization can improve average BLP by 17.1% on average, resulting in a 9.2% reduction in average memory access latency. Furthermore, considering memory controller-level parallelism and row-buffer locality (in addition to BLP) takes our average improvement in memory access latency to 22.2%.

Original languageEnglish (US)
Title of host publicationProceedings - 47th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2014
PublisherIEEE Computer Society
Pages571-582
Number of pages12
EditionJanuary
ISBN (Electronic)9781479969982
DOIs
StatePublished - Jan 15 2015
Event47th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2014 - Cambridge, United Kingdom
Duration: Dec 13 2014Dec 17 2014

Publication series

NameProceedings of the Annual International Symposium on Microarchitecture, MICRO
NumberJanuary
Volume2015-January
ISSN (Print)1072-4451

Other

Other47th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2014
Country/TerritoryUnited Kingdom
CityCambridge
Period12/13/1412/17/14

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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