COMPUTATION AVAILABILITY OF MULTIPLE-BUS MULTIPROCESSORS.

Chitaranjan Das, Laxmi N. Bhuyan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

The effect of failures on the performance of multiple-bus multiprocessors is discussed. Bandwidth expressions for this architecture are derived for uniform and nonuniform memory references. Mathematical models are developed to compute the reliability- and performance-related computation availability. The results obtained for the multiple-bus interconnection are compared with those for a crossbar.

Original languageEnglish (US)
Title of host publicationProceedings of the International Conference on Parallel Processing
EditorsDouglas DeGroot
PublisherIEEE
Pages807-813
Number of pages7
ISBN (Print)0818606371
StatePublished - Dec 1 1985

Publication series

NameProceedings of the International Conference on Parallel Processing
ISSN (Print)0190-3918

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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