The effect of failures on the performance of multiple-bus multiprocessors is discussed. Bandwidth expressions for this architecture are derived for uniform and nonuniform memory references. Mathematical models are developed to compute the reliability- and performance-related computation availability. The results obtained for the multiple-bus interconnection are compared with those for a crossbar.
|Original language||English (US)|
|Title of host publication||Proceedings of the International Conference on Parallel Processing|
|Number of pages||7|
|State||Published - Dec 1 1985|
|Name||Proceedings of the International Conference on Parallel Processing|
All Science Journal Classification (ASJC) codes
- Hardware and Architecture