Due to the growing importance of digital logic testing and fault simulation, a significant need is arising for introducing the basic concepts of fault diagnosis of digital circuits to students in the introductory digital systems design courses. This paper presents a description of an instructional software package (termed Nodes 3) developed at Penn State Altoona Campus and specifically targeted at the fault analysis and simulation aspect of digital system design. Nodes 3 does not merely internally implement a fault analysis algorithm, but rather, it graphically illustrates the steps, and thereby the logical resolution of a fault analysis technique.
|Original language||English (US)|
|Number of pages||8|
|Journal||ASEE Annual Conference Proceedings|
|State||Published - Dec 1 1995|
|Event||Proceedings of the 1995 Annual ASEE Conference. Part 1 (of 2) - Anaheim, CA, USA|
Duration: Jun 25 1995 → Jun 28 1995
All Science Journal Classification (ASJC) codes