TY - GEN
T1 - Computing with ferroelectric FETs
T2 - 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
AU - Aziz, Ahmedullah
AU - Breyer, Evelyn T.
AU - Chen, An
AU - Chen, Xiaoming
AU - Datta, Suman
AU - Gupta, Sumeet Kumar
AU - Hoffmann, Michael
AU - Hu, Xiaobo Sharon
AU - Ionescu, Adrian
AU - Jerry, Matthew
AU - Mikolajick, Thomas
AU - Mulaosmanovic, Halid
AU - Ni, Kai
AU - Niemier, Michael
AU - O'Connor, Ian
AU - Saha, Atanu
AU - Slesazeck, Stefan
AU - Thirumala, Sandeep Krishna
AU - Yin, Xunzhao
N1 - Funding Information:
Datta, Gupta, Hu, and Niemier were supported in part by (i) the center for Low Energy Systems Technology (LEAST), one of six SRC STARnet centers sponsored by MARCO and DARPA, (ii) the National Science Foundation under grant 1640081, and (iii) the Nanoelectronics Research Corporation (NERC), a wholly-owned subsidiary of the SRC, through Extremely Energy Efficient Collective Electronics (EXCEL), an SRC-NRI Nanoelectronics Research Initiative under Research Task ID 2698.004.They also acknowledge SRC GRC. NaMLab was supported by the European Fund for regional Development EFRD and the Free State of Saxony, Europe supports Saxony. They gratefully acknowledge support by GLOBALFOUNDRIES Fab1 LLC and Co. KG, Dresden, Germany. We also thank A. Naeemi and C. Pan.
Publisher Copyright:
© 2018 EDAA.
PY - 2018/4/19
Y1 - 2018/4/19
N2 - In this paper, we consider devices, circuits, and systems comprised of transistors with integrated ferroelectrics. Said structures are actively being considered by various semiconductor manufacturers as they can address a large and unique design space. Transistors with integrated ferroelectrics could (i) enable a better switch (i.e., offer steeper subthreshold swings), (ii) are CMOS compatible, (iii) have multiple operating modes (i.e., I-V characteristics can also enable compact, 1-transistor, non-volatile storage elements, as well as analog synaptic behavior), and (iv) have been experimentally demonstrated (i.e., with respect to all of the aforementioned operating modes). These device-level characteristics offer unique opportunities at the circuit, architectural, and system-level, and are considered here from device, circuit/architecture, and foundry-level perspectives.
AB - In this paper, we consider devices, circuits, and systems comprised of transistors with integrated ferroelectrics. Said structures are actively being considered by various semiconductor manufacturers as they can address a large and unique design space. Transistors with integrated ferroelectrics could (i) enable a better switch (i.e., offer steeper subthreshold swings), (ii) are CMOS compatible, (iii) have multiple operating modes (i.e., I-V characteristics can also enable compact, 1-transistor, non-volatile storage elements, as well as analog synaptic behavior), and (iv) have been experimentally demonstrated (i.e., with respect to all of the aforementioned operating modes). These device-level characteristics offer unique opportunities at the circuit, architectural, and system-level, and are considered here from device, circuit/architecture, and foundry-level perspectives.
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U2 - 10.23919/DATE.2018.8342213
DO - 10.23919/DATE.2018.8342213
M3 - Conference contribution
AN - SCOPUS:85048805345
T3 - Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
SP - 1289
EP - 1298
BT - Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 19 March 2018 through 23 March 2018
ER -