Coping with variations through system-level design

Nilanjan Banerjee, Saumya Chandra, Swaroop Ghosh, Sujit Dey, Anand Raghunathan, Kaushik Roy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Manufacturing and operation-induced variations have emerged as a critical challenge in designing integrated circuits (ICs) under the nanometer technology regime. Most work on addressing variations has focused on device, circuit, and logic-level solutions. As the magnitude of parameter variations increases with technology scaling, these techniques are not sufficient to address the negative impact that variations have on IC performance, power, yield, and design time. Therefore, in recent years, the research community has shown great interest in techniques to address variations starting from the other end of the design process, i.e., at the system level. In this paper, we provide an overview of various techniques that we have developed for coping with variations through system-level design. The presented techniques include a paradigm for designing variationtolerant systems through critical path isolation for timing adaptiveness, application-specific techniques to achieve variation-tolerance by trading off quality of the result, variation-aware system-level power analysis, and system-level power management under variations. These techniques demonstrate that addressing variations during system-level design can greatly mitigate the effects of variations, enabling the design of integrated circuits in scaled technologies.

Original languageEnglish (US)
Title of host publicationProceedings
Subtitle of host publication22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems
Pages581-586
Number of pages6
DOIs
StatePublished - Mar 30 2009
Event22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems - New Delhi, India
Duration: Jan 5 2009Jan 9 2009

Publication series

NameProceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems

Other

Other22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems
CountryIndia
CityNew Delhi
Period1/5/091/9/09

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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    Banerjee, N., Chandra, S., Ghosh, S., Dey, S., Raghunathan, A., & Roy, K. (2009). Coping with variations through system-level design. In Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems (pp. 581-586). [4749733] (Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems). https://doi.org/10.1109/VLSI.Design.2009.96