Correct determination of trap densities at high-k/III-V interfaces

Roman Engel-Herbert, Yoontae Hwang, Varistha Chobpattana, Susanne Stemmer

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The development of high-k/III-V gate stack technology that is compatible with non-planar device geometries is critical to enable next generation low power and high performance logic devices, such as tunneling transistors or MOSFETs using high mobility low band gap III-V semiconductors as channel material. The resurging interest and recent advances integrating high permittivity thin films on III-Vs using atomic layer deposition (ALD) are being reflected in the large number of recent publications addressing the challenges associated. Research efforts towards demonstrating aggressively scaled dielectric films with a low trap density at the high-k/semiconductor interface have been plagued by the difficulties associated with the correct extraction of interface trap density contribution to the admittance response of MOSCAP devices. This paper reviews different methods to determine the interface trap density and its applicability towards correct Dit extraction in high-k/III-V MOSCAPs. InGaAs and GaSb are used to exemplify the potential pitfalls and guidelines are formulated to unambiguously identify Fermi level unpinning.

Original languageEnglish (US)
Title of host publication2013 International Conference on Compound Semiconductor Manufacturing Technology, CS MANTECH 2013
Pages185-188
Number of pages4
StatePublished - 2013
Event28th International Conference on Compound Semiconductor Manufacturing Technology, CS MANTECH 2013 - New Orleans, LA, United States
Duration: May 13 2013May 16 2013

Other

Other28th International Conference on Compound Semiconductor Manufacturing Technology, CS MANTECH 2013
CountryUnited States
CityNew Orleans, LA
Period5/13/135/16/13

Fingerprint

Logic devices
Dielectric films
Atomic layer deposition
Fermi level
Transistors
Energy gap
Permittivity
Semiconductor materials
Thin films
Geometry
III-V semiconductors

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Engel-Herbert, R., Hwang, Y., Chobpattana, V., & Stemmer, S. (2013). Correct determination of trap densities at high-k/III-V interfaces. In 2013 International Conference on Compound Semiconductor Manufacturing Technology, CS MANTECH 2013 (pp. 185-188)
Engel-Herbert, Roman ; Hwang, Yoontae ; Chobpattana, Varistha ; Stemmer, Susanne. / Correct determination of trap densities at high-k/III-V interfaces. 2013 International Conference on Compound Semiconductor Manufacturing Technology, CS MANTECH 2013. 2013. pp. 185-188
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Engel-Herbert, R, Hwang, Y, Chobpattana, V & Stemmer, S 2013, Correct determination of trap densities at high-k/III-V interfaces. in 2013 International Conference on Compound Semiconductor Manufacturing Technology, CS MANTECH 2013. pp. 185-188, 28th International Conference on Compound Semiconductor Manufacturing Technology, CS MANTECH 2013, New Orleans, LA, United States, 5/13/13.

Correct determination of trap densities at high-k/III-V interfaces. / Engel-Herbert, Roman; Hwang, Yoontae; Chobpattana, Varistha; Stemmer, Susanne.

2013 International Conference on Compound Semiconductor Manufacturing Technology, CS MANTECH 2013. 2013. p. 185-188.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Engel-Herbert R, Hwang Y, Chobpattana V, Stemmer S. Correct determination of trap densities at high-k/III-V interfaces. In 2013 International Conference on Compound Semiconductor Manufacturing Technology, CS MANTECH 2013. 2013. p. 185-188