The development of high-k/III-V gate stack technology that is compatible with non-planar device geometries is critical to enable next generation low power and high performance logic devices, such as tunneling transistors or MOSFETs using high mobility low band gap III-V semiconductors as channel material. The resurging interest and recent advances integrating high permittivity thin films on III-Vs using atomic layer deposition (ALD) are being reflected in the large number of recent publications addressing the challenges associated. Research efforts towards demonstrating aggressively scaled dielectric films with a low trap density at the high-k/semiconductor interface have been plagued by the difficulties associated with the correct extraction of interface trap density contribution to the admittance response of MOSCAP devices. This paper reviews different methods to determine the interface trap density and its applicability towards correct Dit extraction in high-k/III-V MOSCAPs. InGaAs and GaSb are used to exemplify the potential pitfalls and guidelines are formulated to unambiguously identify Fermi level unpinning.