Abstract
The development of high-k/III-V gate stack technology that is compatible with non-planar device geometries is critical to enable next generation low power and high performance logic devices, such as tunneling transistors or MOSFETs using high mobility low band gap III-V semiconductors as channel material. The resurging interest and recent advances integrating high permittivity thin films on III-Vs using atomic layer deposition (ALD) are being reflected in the large number of recent publications addressing the challenges associated. Research efforts towards demonstrating aggressively scaled dielectric films with a low trap density at the high-k/semiconductor interface have been plagued by the difficulties associated with the correct extraction of interface trap density contribution to the admittance response of MOSCAP devices. This paper reviews different methods to determine the interface trap density and its applicability towards correct Dit extraction in high-k/III-V MOSCAPs. InGaAs and GaSb are used to exemplify the potential pitfalls and guidelines are formulated to unambiguously identify Fermi level unpinning.
| Original language | English (US) |
|---|---|
| Title of host publication | 2013 International Conference on Compound Semiconductor Manufacturing Technology, CS MANTECH 2013 |
| Pages | 185-188 |
| Number of pages | 4 |
| State | Published - 2013 |
| Event | 28th International Conference on Compound Semiconductor Manufacturing Technology, CS MANTECH 2013 - New Orleans, LA, United States Duration: May 13 2013 → May 16 2013 |
Other
| Other | 28th International Conference on Compound Semiconductor Manufacturing Technology, CS MANTECH 2013 |
|---|---|
| Country | United States |
| City | New Orleans, LA |
| Period | 5/13/13 → 5/16/13 |
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
}
Correct determination of trap densities at high-k/III-V interfaces. / Engel-Herbert, Roman; Hwang, Yoontae; Chobpattana, Varistha; Stemmer, Susanne.
2013 International Conference on Compound Semiconductor Manufacturing Technology, CS MANTECH 2013. 2013. p. 185-188.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Correct determination of trap densities at high-k/III-V interfaces
AU - Engel-Herbert, Roman
AU - Hwang, Yoontae
AU - Chobpattana, Varistha
AU - Stemmer, Susanne
PY - 2013
Y1 - 2013
N2 - The development of high-k/III-V gate stack technology that is compatible with non-planar device geometries is critical to enable next generation low power and high performance logic devices, such as tunneling transistors or MOSFETs using high mobility low band gap III-V semiconductors as channel material. The resurging interest and recent advances integrating high permittivity thin films on III-Vs using atomic layer deposition (ALD) are being reflected in the large number of recent publications addressing the challenges associated. Research efforts towards demonstrating aggressively scaled dielectric films with a low trap density at the high-k/semiconductor interface have been plagued by the difficulties associated with the correct extraction of interface trap density contribution to the admittance response of MOSCAP devices. This paper reviews different methods to determine the interface trap density and its applicability towards correct Dit extraction in high-k/III-V MOSCAPs. InGaAs and GaSb are used to exemplify the potential pitfalls and guidelines are formulated to unambiguously identify Fermi level unpinning.
AB - The development of high-k/III-V gate stack technology that is compatible with non-planar device geometries is critical to enable next generation low power and high performance logic devices, such as tunneling transistors or MOSFETs using high mobility low band gap III-V semiconductors as channel material. The resurging interest and recent advances integrating high permittivity thin films on III-Vs using atomic layer deposition (ALD) are being reflected in the large number of recent publications addressing the challenges associated. Research efforts towards demonstrating aggressively scaled dielectric films with a low trap density at the high-k/semiconductor interface have been plagued by the difficulties associated with the correct extraction of interface trap density contribution to the admittance response of MOSCAP devices. This paper reviews different methods to determine the interface trap density and its applicability towards correct Dit extraction in high-k/III-V MOSCAPs. InGaAs and GaSb are used to exemplify the potential pitfalls and guidelines are formulated to unambiguously identify Fermi level unpinning.
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UR - http://www.scopus.com/inward/citedby.url?scp=84887382720&partnerID=8YFLogxK
M3 - Conference contribution
SN - 1893580210
SN - 9781893580213
SP - 185
EP - 188
BT - 2013 International Conference on Compound Semiconductor Manufacturing Technology, CS MANTECH 2013
ER -