Cost-driven 3D integration with interconnect layers

Xiaoxia Wu, Guangyu Sun, Xiangyu Dong, Reetuparna Das, Yuan Xie, Chitaranjan Das, Jian Li

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Scopus citations

Abstract

The ever increasing die area of Chip Multiprocessors (CMPs) affects manufacturing yield, resulting in higher manufacture cost. Meanwhile, network-on-chip (NoC) has emerged as a promising and scalable solution for interconnecting the cores in CMPs, however it consumes significant portion of the total die area. In this paper, we propose to decouple the interconnect fabric from computing and storage layers, forming a separate layer called Interconnect Service Layer (ISL), in the context of three-dimensional (3D) chip integration. Such decoupling helps reduce the die area for each layer in 3D stacking. ISL itself can integrate multiple superimposed interconnect topologies. More importantly, ISL can be designed, manufactured, and tested as a separate Intellectual Property (IP) component, which supports multiple designs in the computing and storage layers. The resulting methodology also helps support different manufacturing volume in each die of 3D to reduce the overall manufacturing cost. We demonstrate the proposed methodology with an ISL design example and compare to its 2D and 3D counterparts without ISL support. The results show that 3D design with ISL not only provides significant cost reduction, but also achieves power-performance improvement thanks to the efficient usage of ISL.

Original languageEnglish (US)
Title of host publicationProceedings of the 47th Design Automation Conference, DAC '10
Pages150-155
Number of pages6
DOIs
StatePublished - Sep 7 2010
Event47th Design Automation Conference, DAC '10 - Anaheim, CA, United States
Duration: Jun 13 2010Jun 18 2010

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Other

Other47th Design Automation Conference, DAC '10
CountryUnited States
CityAnaheim, CA
Period6/13/106/18/10

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation

Fingerprint Dive into the research topics of 'Cost-driven 3D integration with interconnect layers'. Together they form a unique fingerprint.

  • Cite this

    Wu, X., Sun, G., Dong, X., Das, R., Xie, Y., Das, C., & Li, J. (2010). Cost-driven 3D integration with interconnect layers. In Proceedings of the 47th Design Automation Conference, DAC '10 (pp. 150-155). (Proceedings - Design Automation Conference). https://doi.org/10.1145/1837274.1837313