Abstract
Reverse Engineering (RE) of Intellectual Property (IP) has become increasingly more efficient with sophisticated imaging and probing techniques. Gate camouflaging is a well-known technique used to prevent an adversary from deciphering the chip design and stealing the IP. Several flavors of camouflaging have been previously proposed to thwart RE such as, dummy vias and threshold voltage modulation. However, these techniques are either costly or remain vulnerable to backside probing and sophisticated optical attacks. In this paper, we propose a charge - trap based approach of designing camouflaged circuits, which are resilient to backside probing and optical RE. The camouflaging relies on trapped charges at the gate oxide of the camouflaged gate. It does not require any process change and does not leave any layout-level clue. We propose two multi-function dynamic Charge-Trap-based Camouflaged Gates (CTCG) namely, CTCG2 and CTCG4 that can assume 2 and 4 different logic personalities, respectively. We leverage this camouflaging technique to design an n-stage domino-logic implementation. We perform area, power and delay analysis of CTCG and compare with existing camouflaging techniques. Simulation results show an average delay overhead of 2X, leakage overhead of 3.5X, total power overhead of 2.2X and area overhead of 7.4X with respect to standard dynamic gates. Since CTCG overhead is high and may suffer from leakage of trapped charges if process is not optimized carefully, we propose to replace the charge-trap circuit with a Non-Volatile Ferroelectric FET (NV-FeFET). Simulation results of NV-FeFET based CTCG show an average delay overhead of 1. 7X, leakage overhead of 0.6X, total power overhead of 0.9X and area overhead of 2.3X with respect to standard dynamic gates.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2018 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 103-110 |
| Number of pages | 8 |
| ISBN (Electronic) | 9781538647318 |
| DOIs | |
| State | Published - Jun 12 2018 |
| Event | 2018 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2018 - Washington, United States Duration: Apr 30 2018 → May 4 2018 |
Other
| Other | 2018 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2018 |
|---|---|
| Country | United States |
| City | Washington |
| Period | 4/30/18 → 5/4/18 |
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All Science Journal Classification (ASJC) codes
- Computer Networks and Communications
- Hardware and Architecture
- Safety, Risk, Reliability and Quality
Cite this
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CTCG : Charge-trap based camouflaged gates for reverse engineering prevention. / De, Asmit; Iyengar, Anirudh; Khan, Mohamad Nasim I.; Lin, Sung Hao; Thirumala, Sandeep; Ghosh, Swaroop; Gupta, Sumeet Kumar.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 103-110.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - CTCG
T2 - Charge-trap based camouflaged gates for reverse engineering prevention
AU - De, Asmit
AU - Iyengar, Anirudh
AU - Khan, Mohamad Nasim I.
AU - Lin, Sung Hao
AU - Thirumala, Sandeep
AU - Ghosh, Swaroop
AU - Gupta, Sumeet Kumar
PY - 2018/6/12
Y1 - 2018/6/12
N2 - Reverse Engineering (RE) of Intellectual Property (IP) has become increasingly more efficient with sophisticated imaging and probing techniques. Gate camouflaging is a well-known technique used to prevent an adversary from deciphering the chip design and stealing the IP. Several flavors of camouflaging have been previously proposed to thwart RE such as, dummy vias and threshold voltage modulation. However, these techniques are either costly or remain vulnerable to backside probing and sophisticated optical attacks. In this paper, we propose a charge - trap based approach of designing camouflaged circuits, which are resilient to backside probing and optical RE. The camouflaging relies on trapped charges at the gate oxide of the camouflaged gate. It does not require any process change and does not leave any layout-level clue. We propose two multi-function dynamic Charge-Trap-based Camouflaged Gates (CTCG) namely, CTCG2 and CTCG4 that can assume 2 and 4 different logic personalities, respectively. We leverage this camouflaging technique to design an n-stage domino-logic implementation. We perform area, power and delay analysis of CTCG and compare with existing camouflaging techniques. Simulation results show an average delay overhead of 2X, leakage overhead of 3.5X, total power overhead of 2.2X and area overhead of 7.4X with respect to standard dynamic gates. Since CTCG overhead is high and may suffer from leakage of trapped charges if process is not optimized carefully, we propose to replace the charge-trap circuit with a Non-Volatile Ferroelectric FET (NV-FeFET). Simulation results of NV-FeFET based CTCG show an average delay overhead of 1. 7X, leakage overhead of 0.6X, total power overhead of 0.9X and area overhead of 2.3X with respect to standard dynamic gates.
AB - Reverse Engineering (RE) of Intellectual Property (IP) has become increasingly more efficient with sophisticated imaging and probing techniques. Gate camouflaging is a well-known technique used to prevent an adversary from deciphering the chip design and stealing the IP. Several flavors of camouflaging have been previously proposed to thwart RE such as, dummy vias and threshold voltage modulation. However, these techniques are either costly or remain vulnerable to backside probing and sophisticated optical attacks. In this paper, we propose a charge - trap based approach of designing camouflaged circuits, which are resilient to backside probing and optical RE. The camouflaging relies on trapped charges at the gate oxide of the camouflaged gate. It does not require any process change and does not leave any layout-level clue. We propose two multi-function dynamic Charge-Trap-based Camouflaged Gates (CTCG) namely, CTCG2 and CTCG4 that can assume 2 and 4 different logic personalities, respectively. We leverage this camouflaging technique to design an n-stage domino-logic implementation. We perform area, power and delay analysis of CTCG and compare with existing camouflaging techniques. Simulation results show an average delay overhead of 2X, leakage overhead of 3.5X, total power overhead of 2.2X and area overhead of 7.4X with respect to standard dynamic gates. Since CTCG overhead is high and may suffer from leakage of trapped charges if process is not optimized carefully, we propose to replace the charge-trap circuit with a Non-Volatile Ferroelectric FET (NV-FeFET). Simulation results of NV-FeFET based CTCG show an average delay overhead of 1. 7X, leakage overhead of 0.6X, total power overhead of 0.9X and area overhead of 2.3X with respect to standard dynamic gates.
UR - http://www.scopus.com/inward/record.url?scp=85049989106&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85049989106&partnerID=8YFLogxK
U2 - 10.1109/HST.2018.8383897
DO - 10.1109/HST.2018.8383897
M3 - Conference contribution
SP - 103
EP - 110
BT - Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2018
PB - Institute of Electrical and Electronics Engineers Inc.
ER -