Reverse Engineering (RE) of Intellectual Property (IP) has become increasingly more efficient with sophisticated imaging and probing techniques. Gate camouflaging is a well-known technique used to prevent an adversary from deciphering the chip design and stealing the IP. Several flavors of camouflaging have been previously proposed to thwart RE such as, dummy vias and threshold voltage modulation. However, these techniques are either costly or remain vulnerable to backside probing and sophisticated optical attacks. In this paper, we propose a charge - trap based approach of designing camouflaged circuits, which are resilient to backside probing and optical RE. The camouflaging relies on trapped charges at the gate oxide of the camouflaged gate. It does not require any process change and does not leave any layout-level clue. We propose two multi-function dynamic Charge-Trap-based Camouflaged Gates (CTCG) namely, CTCG2 and CTCG4 that can assume 2 and 4 different logic personalities, respectively. We leverage this camouflaging technique to design an n-stage domino-logic implementation. We perform area, power and delay analysis of CTCG and compare with existing camouflaging techniques. Simulation results show an average delay overhead of 2X, leakage overhead of 3.5X, total power overhead of 2.2X and area overhead of 7.4X with respect to standard dynamic gates. Since CTCG overhead is high and may suffer from leakage of trapped charges if process is not optimized carefully, we propose to replace the charge-trap circuit with a Non-Volatile Ferroelectric FET (NV-FeFET). Simulation results of NV-FeFET based CTCG show an average delay overhead of 1. 7X, leakage overhead of 0.6X, total power overhead of 0.9X and area overhead of 2.3X with respect to standard dynamic gates.