Results are presented on the design, layout, and fabrication of a custom-designed integrated circuit for a residue number system digital filter module. The architecture is based on a ROM-accumulator FIR structure in which the modular arithmetic for each module is realized on a separate chip. The modules are designed to support error detection and fault isolation at module boundaries. Of the five chips that were fabricated and tested, all were found to be fully operational, with three operating at a maximum data-cycle frequency of approximately 1. 7 MHz.
|Original language||English (US)|
|Number of pages||4|
|Journal||ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings|
|State||Published - Dec 1 1985|
All Science Journal Classification (ASJC) codes
- Signal Processing
- Electrical and Electronic Engineering