Data layout optimization for GPGPU architectures

Jun Liu, Wei Ding, Ohyoung Jang, Mahmut Kandemir

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

GPUs are being widely used in accelerating general-purpose applications, leading to the emergence of GPGPU architectures. New programming models, e.g., Compute Unified Device Architecture (CUDA), have been proposed to facilitate programming general-purpose computations in GPGPUs. However, writing high-performance CUDA codes manually is still tedious and difficult. In particular, the organization of the data in the memory space can greatly affect the performance due to the unique features of a custom GPGPU memory hierarchy. In this work, we propose an automatic data layout transformation framework to solve the key issues associated with a GPGPU memory hierarchy (i.e., channel skewing, data coalescing, and bank conflicts). Our approach employs a widely applicable strategy based on a novel concept called data localization. Specifically, we try to optimize the layout of the arrays accessed in affine loop nests, for both the device memory and shared memory, at both coarse grain and fine grain parallelization levels. We performed an experimental evaluation of our data layout optimization strategy using 15 benchmarks on an NVIDIA CUDA GPU device. The results show that the proposed data transformation approach brings around 4.3X speedup on average.

Original languageEnglish (US)
Title of host publicationPPoPP 2013 - Proceedings of the 2013 ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
Pages283-284
Number of pages2
DOIs
StatePublished - Mar 25 2013
Event18th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP 2013 - Shenzhen, China
Duration: Feb 23 2013Feb 27 2013

Publication series

NameProceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP

Other

Other18th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP 2013
CountryChina
CityShenzhen
Period2/23/132/27/13

All Science Journal Classification (ASJC) codes

  • Software

Fingerprint Dive into the research topics of 'Data layout optimization for GPGPU architectures'. Together they form a unique fingerprint.

  • Cite this

    Liu, J., Ding, W., Jang, O., & Kandemir, M. (2013). Data layout optimization for GPGPU architectures. In PPoPP 2013 - Proceedings of the 2013 ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (pp. 283-284). (Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP). https://doi.org/10.1145/2442516.2442546