Data privacy in non-volatile cache: Challenges, attack models and solutions

Nitin Rathi, Swaroop Ghosh, Anirudh Iyengar, Helia Naeimi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

Spin-Transfer-Torque RAM (STTRAM) is considered to be a strong candidate for last level cache (LLC). Although promising STTRAM LLC brings new security challenges that were absent in conventional volatile memories such as Static RAM (SRAM). The root cause is persistent data and the fundamental dependency of the memory technology on ambient parameters such as magnetic field and temperature that can be exploited to compromise the data. We provide a qualitative analysis of the data privacy issues in the emerging nonvolatile cache. We also propose new attack models to compromise the sensitive data in LLC. The encryption technique used to secure data in main memory and hard disk may not be useful for LLC due to latency overhead. We propose two low-overhead techniques to ensure data privacy in LLC-(a) implementing semi nonvolatile memory (SNVM); and, (b) data erasure at power OFF. Erasing could be energy intensive and may require dedicated battery to work under power failure attacks. To address this concern we reuse the energy stored in power rail after power OFF to erase the bits using a canary circuit to track MTJ write time. The simulation results show 0.6% IPC loss and 1.2% energy overhead during normal operation due to added circuitry.

Original languageEnglish (US)
Title of host publication2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages348-353
Number of pages6
ISBN (Electronic)9781467395694
DOIs
StatePublished - Mar 7 2016
Event21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 - Macao, Macao
Duration: Jan 25 2016Jan 28 2016

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume25-28-January-2016

Other

Other21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
CountryMacao
CityMacao
Period1/25/161/28/16

Fingerprint

Data privacy
Random access storage
Data storage equipment
Torque
Hard disk storage
Cryptography
Rails
Magnetic fields
Networks (circuits)
Temperature

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

Cite this

Rathi, N., Ghosh, S., Iyengar, A., & Naeimi, H. (2016). Data privacy in non-volatile cache: Challenges, attack models and solutions. In 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 (pp. 348-353). [7428036] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 25-28-January-2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2016.7428036
Rathi, Nitin ; Ghosh, Swaroop ; Iyengar, Anirudh ; Naeimi, Helia. / Data privacy in non-volatile cache : Challenges, attack models and solutions. 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 348-353 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).
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abstract = "Spin-Transfer-Torque RAM (STTRAM) is considered to be a strong candidate for last level cache (LLC). Although promising STTRAM LLC brings new security challenges that were absent in conventional volatile memories such as Static RAM (SRAM). The root cause is persistent data and the fundamental dependency of the memory technology on ambient parameters such as magnetic field and temperature that can be exploited to compromise the data. We provide a qualitative analysis of the data privacy issues in the emerging nonvolatile cache. We also propose new attack models to compromise the sensitive data in LLC. The encryption technique used to secure data in main memory and hard disk may not be useful for LLC due to latency overhead. We propose two low-overhead techniques to ensure data privacy in LLC-(a) implementing semi nonvolatile memory (SNVM); and, (b) data erasure at power OFF. Erasing could be energy intensive and may require dedicated battery to work under power failure attacks. To address this concern we reuse the energy stored in power rail after power OFF to erase the bits using a canary circuit to track MTJ write time. The simulation results show 0.6{\%} IPC loss and 1.2{\%} energy overhead during normal operation due to added circuitry.",
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Rathi, N, Ghosh, S, Iyengar, A & Naeimi, H 2016, Data privacy in non-volatile cache: Challenges, attack models and solutions. in 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016., 7428036, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 25-28-January-2016, Institute of Electrical and Electronics Engineers Inc., pp. 348-353, 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016, Macao, Macao, 1/25/16. https://doi.org/10.1109/ASPDAC.2016.7428036

Data privacy in non-volatile cache : Challenges, attack models and solutions. / Rathi, Nitin; Ghosh, Swaroop; Iyengar, Anirudh; Naeimi, Helia.

2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 348-353 7428036 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 25-28-January-2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Rathi N, Ghosh S, Iyengar A, Naeimi H. Data privacy in non-volatile cache: Challenges, attack models and solutions. In 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc. 2016. p. 348-353. 7428036. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2016.7428036