Delay and energy efficient data transmission for on-chip buses

Madhu Mutyam, Melvin Eze, Vijaykrishnan Narayanan, Yuan Xie

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Scopus citations

Abstract

On-chip buses in deep sub-micron designs consume significant amounts of power and have large propagation delays. Thus, minimizing power consumption and propagation delay are the most important design objectives. In this paper, we propose a technique for delay and energy efficient data transmission for on-chip buses and evaluate the effectiveness of our technique by focusing on the Ll cache address/data buses of a microprocessor using the SPEC2000 CINT benchmark suit. We show that our technique achieves 31% (30%) of delay improvement along with energy savings of 13% (9%) over the base case for data transmission on address (data) bus.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
Pages355-360
Number of pages6
DOIs
StatePublished - Oct 9 2006
EventIEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006 - Klarlsruhe, Germany
Duration: Mar 2 2006Mar 3 2006

Publication series

NameProceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
Volume2006

Other

OtherIEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
CountryGermany
CityKlarlsruhe
Period3/2/063/3/06

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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