Delay fault localization in test-per-scan BIST using built-in delay sensor

Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Delay failures are becoming a dominant failure mechanism in nanometer technologies. Diagnosis of such failures is important to ensure yield and robustness of the design. However, the increasing circuit size limits the granularity of diagnosis, resulting in large suspect fault list. In this paper, we present a methodology for improving delay fault localization in test-per-scan BIST using on-die delay sensing at selective test points. It is demonstrated that the proposed technique can improve the resolution of fault localization for both transition and segment delay fault models. Experimental results for a set of ISCAS89 benchmarks show upto 49% (82%) average improvement in fault localization for transition (segment) delay fault models. The area overhead due to delay sensing hardware have been limited to 4%.

Original languageEnglish (US)
Title of host publicationProceedings - IOLTS 2006
Subtitle of host publication12th IEEE International On-Line Testing Symposium
Pages31-36
Number of pages6
Volume2006
DOIs
StatePublished - Dec 1 2006
EventIOLTS 2006: 12th IEEE International On-Line Testing Symposium - Como, Italy
Duration: Jul 10 2006Jul 12 2006

Other

OtherIOLTS 2006: 12th IEEE International On-Line Testing Symposium
CountryItaly
CityComo
Period7/10/067/12/06

Fingerprint

Built-in self test
Sensors
Hardware
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering

Cite this

Ghosh, S., Bhunia, S., Raychowdhury, A., & Roy, K. (2006). Delay fault localization in test-per-scan BIST using built-in delay sensor. In Proceedings - IOLTS 2006: 12th IEEE International On-Line Testing Symposium (Vol. 2006, pp. 31-36). [1655512] https://doi.org/10.1109/IOLTS.2006.19
Ghosh, Swaroop ; Bhunia, Swarup ; Raychowdhury, Arijit ; Roy, Kaushik. / Delay fault localization in test-per-scan BIST using built-in delay sensor. Proceedings - IOLTS 2006: 12th IEEE International On-Line Testing Symposium. Vol. 2006 2006. pp. 31-36
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abstract = "Delay failures are becoming a dominant failure mechanism in nanometer technologies. Diagnosis of such failures is important to ensure yield and robustness of the design. However, the increasing circuit size limits the granularity of diagnosis, resulting in large suspect fault list. In this paper, we present a methodology for improving delay fault localization in test-per-scan BIST using on-die delay sensing at selective test points. It is demonstrated that the proposed technique can improve the resolution of fault localization for both transition and segment delay fault models. Experimental results for a set of ISCAS89 benchmarks show upto 49{\%} (82{\%}) average improvement in fault localization for transition (segment) delay fault models. The area overhead due to delay sensing hardware have been limited to 4{\%}.",
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Ghosh, S, Bhunia, S, Raychowdhury, A & Roy, K 2006, Delay fault localization in test-per-scan BIST using built-in delay sensor. in Proceedings - IOLTS 2006: 12th IEEE International On-Line Testing Symposium. vol. 2006, 1655512, pp. 31-36, IOLTS 2006: 12th IEEE International On-Line Testing Symposium, Como, Italy, 7/10/06. https://doi.org/10.1109/IOLTS.2006.19

Delay fault localization in test-per-scan BIST using built-in delay sensor. / Ghosh, Swaroop; Bhunia, Swarup; Raychowdhury, Arijit; Roy, Kaushik.

Proceedings - IOLTS 2006: 12th IEEE International On-Line Testing Symposium. Vol. 2006 2006. p. 31-36 1655512.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AB - Delay failures are becoming a dominant failure mechanism in nanometer technologies. Diagnosis of such failures is important to ensure yield and robustness of the design. However, the increasing circuit size limits the granularity of diagnosis, resulting in large suspect fault list. In this paper, we present a methodology for improving delay fault localization in test-per-scan BIST using on-die delay sensing at selective test points. It is demonstrated that the proposed technique can improve the resolution of fault localization for both transition and segment delay fault models. Experimental results for a set of ISCAS89 benchmarks show upto 49% (82%) average improvement in fault localization for transition (segment) delay fault models. The area overhead due to delay sensing hardware have been limited to 4%.

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Ghosh S, Bhunia S, Raychowdhury A, Roy K. Delay fault localization in test-per-scan BIST using built-in delay sensor. In Proceedings - IOLTS 2006: 12th IEEE International On-Line Testing Symposium. Vol. 2006. 2006. p. 31-36. 1655512 https://doi.org/10.1109/IOLTS.2006.19