Demonstration of p-type In0.7Ga0.3As/GaAs0.35Sb0.65 and n-type GaAs0.4Sb0.6/In0.65Ga0.35As complimentary Heterojunction Vertical Tunnel FETs for ultra-low power logic

R. Pandey, H. Madan, H. Liu, V. Chobpattana, M. Barth, B. Rajamohanan, M. J. Hollander, T. Clark, K. Wang, J. H. Kim, D. Gundlach, K. P. Cheung, J. Suehle, R. Engel-Herbert, S. Stemmer, S. Datta

Research output: Chapter in Book/Report/Conference proceedingConference contribution

39 Scopus citations

Abstract

Extremely scaled high-k gate dielectrics with high quality electrical interfaces with arsenide (As) and antimonide (Sb) channels are used to demonstrate complimentary 'all III-V' Heterojunction Vertical Tunnel FET (HVTFET) with record performance at -VDS=0.5V. The p-type TFET (PTFET) has ION =30μA/μm and ION/IOFF =105, whereas the n-type TFET (NTFET) has ION =275μA/μm and ION/IOFF=3×105, respectively. NTFET shows 55mV/decade switching slope (SS) while PTFET shows 115mV/decade SS in pulsed mode measurement. Vertical TFET offers 77% higher effective drive strength than Si-FinFET for given inverter standard cell area. Energy-delay performance of TFET shows gain over CMOS for low VDD logic applications.

Original languageEnglish (US)
Title of host publication2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
PagesT206-T207
Volume2015-August
ISBN (Electronic)9784863485013
DOIs
StatePublished - Aug 25 2015
EventSymposium on VLSI Technology, VLSI Technology 2015 - Kyoto, Japan
Duration: Jun 16 2015Jun 18 2015

Other

OtherSymposium on VLSI Technology, VLSI Technology 2015
CountryJapan
CityKyoto
Period6/16/156/18/15

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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