Resistive Random Access Memory (RRAM) based PUF designs exploit either the probabilistic switching or the resistance variability during forming, SET and RESET processes of RRAM. Memory PUFs using RRAM are typically weak PUFs due to fewer number of challenge response pairs. We propose strong arbiter PUF based on 1T-1R bit cell which is obtained from conventional RRAM memory array with minimally invasive changes. Conventional voltage sense amplifier is repurposed to act like an arbiter and generate the response. Similarly, address and data lines are repurposed to act as challenge and response respectively. The PUF is simulated using 65nm predictive technology models for CMOS and Verilog-A model for a hafnium oxide based RRAM. The proposed PUF architecture is evaluated for uniqueness, uniformity and reliability and by running NIST benchmarks for various number of stages. It demonstrates mean intra-die Hamming Distance (HD) of 0.13% and inter-die HD of 51.3%, and passes the NIST tests. We study the vulnerability of proposed PUF to machine learning attacks. We also present an application of proposed PUF for data attestation in the internet of things. Proposed PUF-based data attestation consumes 9.88pJ of total energy per data block of 64-bits and offers a speed of 120.7kbps.
|Original language||English (US)|
|Journal||IEEE Transactions on Dependable and Secure Computing|
|State||Accepted/In press - Aug 20 2018|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering