Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs

Reetuparna Das, Soumya Eachempati, Asit K. Mishra, Vijaykrishnan Narayanan, Chita R. Das

Research output: Chapter in Book/Report/Conference proceedingConference contribution

145 Scopus citations

Abstract

Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Both these parameters can also be optimized by application induced communication locality since applications mapped on a large CMP system will benefit from clustered communication, where data is placed in cache banks closer to the cores accessing it. Thus, in this paper, we design a hierarchical network topology that takes advantage of such communication locality. The two-tier hierarchical topology consists of local networks that are connected via a global network. The local network is a simple, high-bandwidth, low-power shared bus fabric, and the global network is a low-radix mesh. The key insight that enables the hybrid topology is that most communication in CMP applications can be limited to the local network, and thus, using a fast, low-power bus to handle local communication will improve both packet latency and power-efficiency. The proposed hierarchical topology provides up to 63% reduction in energy-delayproduct over mesh, 47% over flattened butterfly, and 33% with respect to concentrated mesh across network sizes with uniform and non-uniform synthetic traffic. For real parallel workloads, the hybrid topology provides up to 14% improvement in system performance (IPC) and in terms of energy-delay-product, improvements of 70%, 22%, 30% over the mesh, flattened butterfly, and concentrated mesh, respectively, for a 32-way CMP. Although the hybrid topology scales in a power- and bandwidthefficient manner with network size, while keeping the average packet latency low in comparison to high radix topologies, it has lower throughput due to high concentration. To improve the throughput of the hybrid topology, we propose a novel router microarchitecture, called XShare, which exploits data value locality and bimodal traffic characteristics of CMP applications to transfer multiple small flits over a single channel. This helps in enhancing the network throughput by 35%, providing a latency reduction of 14% with synthetic traffic, and improving IPC on an average 4% with application workloads.

Original languageEnglish (US)
Title of host publicationProceedings - 15th International Symposium on High-Performance Computer Architecture, HPCA - 15 2009
Pages175-186
Number of pages12
DOIs
StatePublished - Apr 24 2009
Event2008 IEEE International Conference on Mechatronics and Automation, ICMA 2008 - Takamatsu, Japan
Duration: Aug 5 2008Aug 8 2008

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
ISSN (Print)1530-0897

Other

Other2008 IEEE International Conference on Mechatronics and Automation, ICMA 2008
CountryJapan
CityTakamatsu
Period8/5/088/8/08

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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  • Cite this

    Das, R., Eachempati, S., Mishra, A. K., Narayanan, V., & Das, C. R. (2009). Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. In Proceedings - 15th International Symposium on High-Performance Computer Architecture, HPCA - 15 2009 (pp. 175-186). [4798252] (Proceedings - International Symposium on High-Performance Computer Architecture). https://doi.org/10.1109/HPCA.2009.4798252