Design and implementation of double base integer encoder in the flash ADC

Son Nguyen Minh, Kim Jongsoo, Kim Insoo, Choi Kyusun

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The DBNR (Double Base Number Representation) has been known to represent the Multidimensional Logarithmic Number System for implementing the multiplier accumulator architecture of DSP (Digital Signal Processing). This paper also uses the DBNR to improve the bottleneck of DSP arithmetic circuits with the flash ADC (Analog-to-Digital Converter). The Constraint algorithm is suggested to solve fan-in problem of the Greedy algorithm in designing encoder circuit of the flash ADC. The Constraint algorithm shows better performance in terms of layout area, power consumption, and operation speed, compared with the FAT tree encoder, which is known as the fastest encoder circuit yielding binary output.

Original languageEnglish (US)
Title of host publication2009 6th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, ECTI-CON 2009
Pages496-499
Number of pages4
DOIs
StatePublished - Oct 22 2009
Event2009 6th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, ECTI-CON 2009 - Chonburi, Thailand
Duration: May 6 2009May 9 2009

Publication series

Name2009 6th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, ECTI-CON 2009
Volume1

Other

Other2009 6th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, ECTI-CON 2009
CountryThailand
CityChonburi
Period5/6/095/9/09

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering

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  • Cite this

    Minh, S. N., Jongsoo, K., Insoo, K., & Kyusun, C. (2009). Design and implementation of double base integer encoder in the flash ADC. In 2009 6th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, ECTI-CON 2009 (pp. 496-499). [5137056] (2009 6th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, ECTI-CON 2009; Vol. 1). https://doi.org/10.1109/ECTICON.2009.5137056