Design and implementation of flash ADC and DBNS FIR filter

Minh Son Nguyen, Jongsoo Kim, Insoo Kim, Kuysun Choi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

Digital signal processing (DSP) system has been widely used in telecommunication, audio, video, avionics, bio-medical instruments, and portable electronic products. However, DSP needs fast multipliers and adders to process signals at real time. The Double Base Number System (DBNS) can process arithmetic operation fast due to the multidimensional logarithmic number feature, which is suitable for multiplier accumulator architecture of DSP. This system can reduce the hardware complexity by inner product operation. This paper uses the DBNS to improve the DSP arithmetic operation speed with the flash ADC. A 6-bit flash ADC is designed with the 0.18 μm CMOS technology. The HSPICE simulation of proposed coding technique shows 11% and 100% improvement in speed compared with FAT tree encoder and ROM based encoder respectively. In addition, the circuit saved up to 8.16% and 174.85% in power consumption.

Original languageEnglish (US)
Title of host publication2009 International SoC Design Conference, ISOCC 2009
Pages325-328
Number of pages4
DOIs
StatePublished - Dec 1 2009
Event2009 International SoC Design Conference, ISOCC 2009 - Busan, Korea, Republic of
Duration: Nov 22 2009Nov 24 2009

Publication series

Name2009 International SoC Design Conference, ISOCC 2009

Other

Other2009 International SoC Design Conference, ISOCC 2009
CountryKorea, Republic of
CityBusan
Period11/22/0911/24/09

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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