DESIGN AND IMPLEMENTATION OF REAL TIME VIDEO PROCESSOR.

Shisphal Rawat, Poras T. Balsara, Mary Jane Irwin, Tom Mackowiak

Research output: Contribution to journalConference article

Abstract

The authors describe the design and implementation of an arithmetic unit for a video filter. The central unit of the video filter consists of six identical chips called common arithmetic units (CAUs), each of which contains three common arithmetic cells (CACs). These 64-pin CAUs are assembled on a board in a pipelined architecture to realize real-time performance. The throughput rate for the chip is 11. 3 Mhz. A constant-time pipelined adder design has been proposed and implemented. The absolute delay is still O(log n). The area O(n log n and absolute delay O(log n) for the adder are within a constant factor of the optimal bounds.

Original languageEnglish (US)
Pages (from-to)2215-2218
Number of pages4
JournalICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
StatePublished - Dec 1 1986

All Science Journal Classification (ASJC) codes

  • Software
  • Signal Processing
  • Electrical and Electronic Engineering

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