The authors describe the design and implementation of an arithmetic unit for a video filter. The central unit of the video filter consists of six identical chips called common arithmetic units (CAUs), each of which contains three common arithmetic cells (CACs). These 64-pin CAUs are assembled on a board in a pipelined architecture to realize real-time performance. The throughput rate for the chip is 11. 3 Mhz. A constant-time pipelined adder design has been proposed and implemented. The absolute delay is still O(log n). The area O(n log n and absolute delay O(log n) for the adder are within a constant factor of the optimal bounds.
|Original language||English (US)|
|Number of pages||4|
|Journal||ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings|
|State||Published - 1986|
All Science Journal Classification (ASJC) codes
- Signal Processing
- Electrical and Electronic Engineering