The rapid development in wireless networking has been witnessed in past several years, which aimed on high speed and long range applications. The increasing demand for low data and low power networking led to the development of ZigBee technology. This technology was developed for Wireless Personal Area Networks (WPAN), directed at control and military applications, where low cost, low data rate, and more battery life were main requirements. ZigBee is a standard, which defines set of communication protocols. ZigBee based devices operate in 868 MHz, 915 MHz and 2.4 GHz frequency bands. It has maximum data rate of 250K bits per second. This paper explores the architectural blocks of digital ZigBee transmitter. The advancement in VLSI technology led to the development of more efficient, accurate, small, and fast design. ZigBee has potential application in Internet of Things (IoT), because of the fact that it is a low power and low data rate device. The main focus of the project is to design a ZigBee transmitter using Verilog for IoT applications. A basic digital ZigBee transmitter consists of cyclic redundancy check, Bit-to-Symbol block, Symbol-to-Chip block, and a Modulator. This paper presents digital design and Verilog-HDL simulation of the Cyclic Redundancy Check and Bit-to-Symbol block of the ZigBee transmitter.