The charge recovery databus is a scheme which reduce energy consumption through the application of adiabatic circuit techniques. Previous work  gives a solid theoretical analysis of this scheme, including quantitative data assuming random bus values. We extend this earlier work by presenting a quantitative analysis of the charge recovery databus using 15 benchmarks and four high-level bus coding schemes. We show that a very simple implementation of the charge recovery databus is capable of reducing average energy consumption by 28% beyond traditional high-level bus encoding techniques. In addition, we examine delay and energy consumption in the added hardware.
|Original language||English (US)|
|Number of pages||3|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|State||Published - Feb 2001|
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering