Design issues in digit serial signal processors

Mary Jane Irwin, Robert Michael Owens

Research output: Contribution to journalConference article

14 Citations (Scopus)

Abstract

Several design issues that have arisen during the development of a set of CAD tools used to support the rapid prototyping of a family of VLSI signal processing architectures are presented. The components out of which the signal processors are constructed are ones which operate digit-serially. Digit-serial architectures, which have digit-serial data transmission combined with digit-serial computation, are uniquely suited for the design of VLSI signal processors. The speed disadvantages of digit-serial input are overcome if the input is overlapped with the computation (referred to as digit pipelining). Thus, digit-serial architectures can provide both high throughput and low latency. Design tradeoffs affecting the component design as well as the system design for digit serial signal processors are presented. Considerations which have affected the development of our CAD tools are discussed.

Original languageEnglish (US)
Pages (from-to)441-444
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume1
StatePublished - Dec 1 1989
EventIEEE International Symposium on Circuits and Systems 1989, the 22nd ISCAS. Part 1 - Portland, OR, USA
Duration: May 8 1989May 11 1989

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Computer aided design
Rapid prototyping
Data communication systems
Signal processing
Systems analysis
Throughput

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Irwin, Mary Jane ; Owens, Robert Michael. / Design issues in digit serial signal processors. In: Proceedings - IEEE International Symposium on Circuits and Systems. 1989 ; Vol. 1. pp. 441-444.
@article{a372e463b30044ac814a39d61ecc103f,
title = "Design issues in digit serial signal processors",
abstract = "Several design issues that have arisen during the development of a set of CAD tools used to support the rapid prototyping of a family of VLSI signal processing architectures are presented. The components out of which the signal processors are constructed are ones which operate digit-serially. Digit-serial architectures, which have digit-serial data transmission combined with digit-serial computation, are uniquely suited for the design of VLSI signal processors. The speed disadvantages of digit-serial input are overcome if the input is overlapped with the computation (referred to as digit pipelining). Thus, digit-serial architectures can provide both high throughput and low latency. Design tradeoffs affecting the component design as well as the system design for digit serial signal processors are presented. Considerations which have affected the development of our CAD tools are discussed.",
author = "Irwin, {Mary Jane} and Owens, {Robert Michael}",
year = "1989",
month = "12",
day = "1",
language = "English (US)",
volume = "1",
pages = "441--444",
journal = "Proceedings - IEEE International Symposium on Circuits and Systems",
issn = "0271-4310",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

Design issues in digit serial signal processors. / Irwin, Mary Jane; Owens, Robert Michael.

In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 1, 01.12.1989, p. 441-444.

Research output: Contribution to journalConference article

TY - JOUR

T1 - Design issues in digit serial signal processors

AU - Irwin, Mary Jane

AU - Owens, Robert Michael

PY - 1989/12/1

Y1 - 1989/12/1

N2 - Several design issues that have arisen during the development of a set of CAD tools used to support the rapid prototyping of a family of VLSI signal processing architectures are presented. The components out of which the signal processors are constructed are ones which operate digit-serially. Digit-serial architectures, which have digit-serial data transmission combined with digit-serial computation, are uniquely suited for the design of VLSI signal processors. The speed disadvantages of digit-serial input are overcome if the input is overlapped with the computation (referred to as digit pipelining). Thus, digit-serial architectures can provide both high throughput and low latency. Design tradeoffs affecting the component design as well as the system design for digit serial signal processors are presented. Considerations which have affected the development of our CAD tools are discussed.

AB - Several design issues that have arisen during the development of a set of CAD tools used to support the rapid prototyping of a family of VLSI signal processing architectures are presented. The components out of which the signal processors are constructed are ones which operate digit-serially. Digit-serial architectures, which have digit-serial data transmission combined with digit-serial computation, are uniquely suited for the design of VLSI signal processors. The speed disadvantages of digit-serial input are overcome if the input is overlapped with the computation (referred to as digit pipelining). Thus, digit-serial architectures can provide both high throughput and low latency. Design tradeoffs affecting the component design as well as the system design for digit serial signal processors are presented. Considerations which have affected the development of our CAD tools are discussed.

UR - http://www.scopus.com/inward/record.url?scp=0024929640&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0024929640&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0024929640

VL - 1

SP - 441

EP - 444

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

SN - 0271-4310

ER -