Design issues in digit serial signal processors

Mary Jane Irwin, Robert Michael Owens

Research output: Contribution to journalConference articlepeer-review

14 Scopus citations

Abstract

Several design issues that have arisen during the development of a set of CAD tools used to support the rapid prototyping of a family of VLSI signal processing architectures are presented. The components out of which the signal processors are constructed are ones which operate digit-serially. Digit-serial architectures, which have digit-serial data transmission combined with digit-serial computation, are uniquely suited for the design of VLSI signal processors. The speed disadvantages of digit-serial input are overcome if the input is overlapped with the computation (referred to as digit pipelining). Thus, digit-serial architectures can provide both high throughput and low latency. Design tradeoffs affecting the component design as well as the system design for digit serial signal processors are presented. Considerations which have affected the development of our CAD tools are discussed.

Original languageEnglish (US)
Pages (from-to)441-444
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume1
StatePublished - Dec 1 1989
EventIEEE International Symposium on Circuits and Systems 1989, the 22nd ISCAS. Part 1 - Portland, OR, USA
Duration: May 8 1989May 11 1989

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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