Design methodologies for high density domain wall memory

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15 Scopus citations

Abstract

Domain wall memory (DWM) has emerged as a possible candidate for embedded cache application. The fundamental advantage of DWM is its MLC (multi-level cell) capability allowing it to store multiple bits/cell in order to break the density barrier. Additionally, it provides low standby power, fast access time, good endurance and good retention. In this paper, we address design challenges associated with DWM for potential use in on-chip cache.

Original languageEnglish (US)
Title of host publicationProceedings of the 2013 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2013
Pages30-31
Number of pages2
DOIs
StatePublished - Nov 6 2013
Event2013 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2013 - New York City, NY, United States
Duration: Jul 15 2013Jul 17 2013

Other

Other2013 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2013
CountryUnited States
CityNew York City, NY
Period7/15/137/17/13

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All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Ghosh, S. (2013). Design methodologies for high density domain wall memory. In Proceedings of the 2013 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2013 (pp. 30-31). [6623035] https://doi.org/10.1109/NanoArch.2013.6623035