Design of a dynamic priority-based fast path architecture for on-chip interconnects

Dongkook Park, Reetuparna Das, Chrysostomos Nicopoulos, Jongman Kim, Vijaykrishnan Narayanan, Ravishankar Iyer, Chitaranjan Das

Research output: Chapter in Book/Report/Conference proceedingConference contribution

37 Scopus citations

Abstract

In modern multi-core System-on-Chip (SoC) architectures, the design of innovative interconnection fabrics is indispensable. The concept of the Network-on-Chip (NoC) architecture has been proposed recently to better suit this requirement. Especially, the router architecture has a significant effect on the overall performance and energy consumption of the chip. We propose a dynamic path management scheme that exploits network traffic information during switch arbitration. Consequently, flits transferred across frequently used paths are expedited by traversing a reduced router pipeline. This technique, based on pipeline bypassing, is simulated and evaluated in terms of network latency and average power consumption. Simulation results with real-world application traces show that the architecture improves the performance up to 30% while incurring only minimal area / power overhead.

Original languageEnglish (US)
Title of host publicationProceedings - 15th Annual IEEE Symposium on High-Performance Interconnects, HOT Interconnects
Pages15-20
Number of pages6
DOIs
StatePublished - Dec 1 2007
Event15th Annual IEEE Symposium on High-Performance Interconnects, HOT Interconnects - Stanford, CA, United States
Duration: Aug 22 2007Aug 24 2007

Other

Other15th Annual IEEE Symposium on High-Performance Interconnects, HOT Interconnects
CountryUnited States
CityStanford, CA
Period8/22/078/24/07

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Park, D., Das, R., Nicopoulos, C., Kim, J., Narayanan, V., Iyer, R., & Das, C. (2007). Design of a dynamic priority-based fast path architecture for on-chip interconnects. In Proceedings - 15th Annual IEEE Symposium on High-Performance Interconnects, HOT Interconnects (pp. 15-20). [4296803] https://doi.org/10.1109/HOTI.2007.1