Design of a nanosensor array architecture

Wei Xu, Vijaykrishnan Narayanan, Y. Xie, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

This paper describes a nanowire sensor array architecture for high-speed, high-accuracy sensor systems. The chip has very simple processing elements (PEs) in a massively parallel architecture, in which each PE is directly connected to seven sensors. A sampling rate of 100 ns is enough to realized high-speed sensing feedback for electronic nose. We aim to create a very simple architecture, because a compact design is required to integrate as many PEs as possible on a single chip. A widely used, easy to implement estimator - minimum distance classifier is introduced to realize the pattern recognition. A sample design is implemented in VHDL and has been simulated and synthesized using TSMC 0.25 standard cell library and a commercial 0.16 standard cell library.

Original languageEnglish (US)
Title of host publicationProceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004
Subtitle of host publicationVLSI in the Nanometer Era
Pages298-303
Number of pages6
StatePublished - Jun 28 2004
EventProceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era - Boston, MA, United States
Duration: Apr 26 2004Apr 28 2004

Other

OtherProceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era
CountryUnited States
CityBoston, MA
Period4/26/044/28/04

Fingerprint

Nanosensors
Processing
Computer hardware description languages
Parallel architectures
Sensors
Sensor arrays
Nanowires
Pattern recognition
Classifiers
Sampling
Feedback

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Xu, W., Narayanan, V., Xie, Y., & Irwin, M. J. (2004). Design of a nanosensor array architecture. In Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era (pp. 298-303)
Xu, Wei ; Narayanan, Vijaykrishnan ; Xie, Y. ; Irwin, Mary Jane. / Design of a nanosensor array architecture. Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era. 2004. pp. 298-303
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Xu, W, Narayanan, V, Xie, Y & Irwin, MJ 2004, Design of a nanosensor array architecture. in Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era. pp. 298-303, Proceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era, Boston, MA, United States, 4/26/04.

Design of a nanosensor array architecture. / Xu, Wei; Narayanan, Vijaykrishnan; Xie, Y.; Irwin, Mary Jane.

Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era. 2004. p. 298-303.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Xu W, Narayanan V, Xie Y, Irwin MJ. Design of a nanosensor array architecture. In Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era. 2004. p. 298-303